• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.6
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• pp.1032-1039
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• 2015

Service function chaining(SFC) defines the creation of network services that consist of an ordered set of service function. A multiple service function instances should be deployed across networks for scalable and fault-tolerant SFC services. Therefore, an incoming flows should be distributed to multiple service function instances appropriately. In this paper, we formulate the flow distribution problem in SFC aiming at minimizing the end-to-end flow latency under resource constraints. Then, we evaluate its optimal solution in a realistic network topology generated by the GT-ITM topology generator. Simulation results reveal that the optimal solution can reduce the total flow latency significantly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.12
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• pp.1314-1317
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• 2014

In this letter, we designed monopole microstrip antenna for WLAN / WiMAX system. The monopole antenna is designed by FR-4 substrate with size is $30mm{\times}40mm$. The proposed antenna is based on a planar monopole design which cover WLAN and WiMAX frequency bands. To obtainthe optimized parameters, we used the simulator, CST's Microwave Studio Program and found the parameters that greatly effect antenna characteristics. Using the obtained parameters, the antenna is designed. Thus the proposed antenna satisfied the -10 dB impedance bandwidth requirement while simultaneously covering the WLAN and WiMAX bands. And characteristics of gain and radiation patterns are obtained for WLAN/WiMAX frequency bands.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.66-76
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• 1998

In this paper, we implement a buffer capable of handling short loops references to statistically lower the miss rate of variable-length instructions stored in the instruction buffer. MAU(Mark Appending Unit) takes the instructions as they are fetched from external memory, performs some initial decode operations and stores the results of the decode in the buffer for reducing multiple decodes when instructions are executed repeatedly such as in a loop. It includes a decision block of whether hit or not for effectively processing branch instructions Each module of the proposed architecture of processing variable-length instruction is described in VHDL structurally and behaviorally and whether it is working well or not is checked on V-System simulator of Model Technology Inc. We synthesized and simulated the architecture using an ASIC Synthesizer tool with 0.6$\mu\textrm{m}$ 5-Volt CMOS COMPASS library. Operation speed is up to 140MHz. The architecture includes about 17,000 gates.

• The Journal of the Acoustical Society of Korea
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• v.14 no.5
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• pp.63-73
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• 1995

The conventional acoustic sounds can be synthesized by Frequency Modulation which includes the variation of frequency, amplitude, and modulation index. In this paper the number of variable synthesis parameters are limited to easily implement the existing two carrier FM algorithm by hardware. The DSP(Digital Signal Processor), which is able to carry out the modified algorithm and synthesize 16 sounds at a time, is designed with $0.8{\mu}m$ standard sells. The DSP which can synthesize 2 sounds at a time is implemented by ASIC emulator to examine the sound quality of the designed DSP. Through the objective and subjective estimation, it is confirmed that the sounds of many instruments from the implemented DSP are very closed to their real sound. Finally the designed DSP is layouted and simulated by VLSI desgn tool. According to the simulation, the designed DSP has the sufficiently fast speed for synthesizing 16 sounds at a time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of Energy Engineering
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• v.23 no.4
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• pp.223-229
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• 2014

This study investigated the explosion characteristics of HCNG fuel using a simulation tool. The damage caused by the storage container explosion and vapor cloud explosion in a gas station was predicted. In case of an vapor cloud explosion in the HCNG station, 50~200kPa explosion pressure was predicted inside the station. When the cylinder explosion was occurred, in case of hydrogen, the measured influential distance of overpressure was 59m and radiant heat was 75m. In case of CNG, influential distance of overpressure was 89m and radiant heat was 144m would be estimated. In case of 30% HCNG that was blended with hydrogen and CNG, influential distance of overpressure was 81m and radiant heat was 130m were measured. The damage distance that explosive overpressure and radiant heat influenced CNG was seen as the highest. HCNG that was placed between CNG and hydrogen tended to be seen as more similar with CNG.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.341-346
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• 2014

This paper has presented the design and fabrication of phase correlator for wideband digital frequency discriminator (DFD) operating over the 6.0 to 18.0 GHz frequency range. Fabricated DFD phase correlator has been measured I or Q output signal, and analyzed frequency discrimination error. The operation of the proposed mixer type correlator has been analyzed by deriving some analytic equations. To design the phase correlator, this paper has modeled and simulated IQ mixer and 8-way power divider by using RF simulation tool. Designed phase correlator has fabricated and measured. The phase error and frequency discrimination error have been presented using by measured I and Q output signal. Over the 6.0~18.0 GHz range, the root mean square(RMS) phase error is $4.81^{\circ}$, RMS and frequency discrimination error is 1.49 MHz, RMS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.