• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.16 no.4 s.95
• /
• pp.366-372
• /
• 2005

This paper presents analysis of a slot array antenna having a low side lobe level and high front-to-back ratio for a repeater system of a satellite DMB(Digital Multimedia Broadcasting) service. Antennas for this repeater system require a high gain and enough isolation to reduce interferences between signals in system. Therefore, it is necessary to suppress a side lobe level and to increase front-to-back ratio. Unlike a structure 134 by lossy microstrip lines, in this work a single cavity-backed slot antenna array using a single waveguide feed is proposed to obtain the reliability for high power handling and high radiation efficiency. The side lobe level and front-to-back ratio are enhanced with tapered array technique and an optimized vertical reflector. The measured side lobe levels in H- and E-plane are under $-33.24\;\cal{dB}$ and $-35.78\;\cal{dB}$, respectively. The front-to-back ratio over $37.84\;\cal{dB}$, and the peak gain of over $17\;\cal{dBi}$ are measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.7
• /
• pp.785-790
• /
• 2008

In this paper, a new balun is proposed. This proposed balun has a DGS(Defected Ground Structure) pattern on the ground plane. The transmission-line is transformed by microstrip-to-slotline transition. DGS pattern on the ground plane and transition of the lines can be easily made a property of the balun. Resonance frequency of the DGS leads to operating frequency of the balun. Also the transition produces $180^{\circ}$ out-of-phase between two output ports without additional transmission line. In this paper, a new balun with VPDGS(Vertically Periodic Defected Ground Structure) effectively lower the operating frequency. To validate the proposed design method, the new balun is designed, fabricated and measured at 2 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.12
• /
• pp.1673-1678
• /
• 2019

There are various networks and communication methods are used in industrial communication. Enterprises need to convert communications between industrial devices and networks for production line expansion, factory upgrades, network segmentation, and SI. This requires designers manufactured by many manufacturers to provide communication equipment for data or protocol conversion in order to connect and transmit various other mechanical devices to the network. This paper designed industrial communication gateway that can support the transformation of industrial communication protocol using multi-layered communication module. Industrial communication gateways have a structure that connects individual communication modules using RS485 communication to multiple layers. Each communication module consisted of analog and digital data card, LAN, and CAN-enabled card. The main board processor used Atmega micro-processor, and the RS485 slot was placed to have a multi-layer communication module structure. These additive layer type communication modules support analog and digital I/O functions and LAN and CAN for wide use in industrial communication control and monitoring.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.47 no.1
• /
• pp.69-76
• /
• 2010

We describe an all-optical circuit which recognizes the header information of packet-by-packet in the access networks based on FTTH. The circuit's operation is confirmed by an experiment in the recognition of 3 and 4 header bits. The output from the header recognition circuit appears in a signal assigned in the time axis according to the header information. The recognition circuit of header for self-routing has a very simple structure using only delay lines and switches. The circuit is expected that it can be constructed of the high reliability and the low cost. Also, the circuit can solve the problems of the power loss and private security which is the weak point of the TDM-PON method by being established a unique transmission line to each subscriber.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.8
• /
• pp.299-307
• /
• 2013

In this paper, design of UWB Antenna which propagate impulse by pulse fidelity and distortion equation was induced and applied. UWB Antenna which has directional characteristic in UWB band should have low radiation loss and impulse radiation distortion. As a result, the paper designed wide band impedance transformer and microstrip slotline transit region structured antenna feeder line. By using the fabricated UWB antenna, the radiation pattern was measured in the radio anechoic chamber. Pulse fidelity of impulse radiation show good results more than 93% within ${\pm}30^{\circ}$ beam width.

• The KIPS Transactions:PartC
• /
• v.14C no.4
• /
• pp.383-388
• /
• 2007

In this paper, we propose a new signal frame structure based on Alamouti code that can maintain the same performance as Alamouti code and increase spectral efficiency. The proposed signal frame structure can increase spectrum efficiency to approach 1(bit/s/Hz) since it can process n bit data during (n+1) time slot. In order to verify two performances, we derive closed form BER via mathematical approach, and compare with the simulation result in Rayleigh fading plus AWGN channel. Then we find that the two performances are exactly same.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.9
• /
• pp.52-59
• /
• 2009

In this paper, the planar waveguide slotted array antenna is presented, which has the 3-layered structure of feeding networks for a high gain. Due to the ionosphere which generates 'Faraday rotation', the skew is happened between the signal radiated from an artificial satellite and the receiving antenna. This causes a polarization loss. In this paper, to remove this polarization loss, the dumbbell shaped linear polarizer using a single layer film is proposed. The gain of proposed antenna is 29.4dB.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.6
• /
• pp.489-493
• /
• 1999

In this paper, an analysis of microstrip-slotline transition is performed using a 3D vector Finite Element Method(FEM). Artificial anistropic absorber technique is employed to implement an matching boundary condition in FEM. On the base of the analysis, power divider/combiner is designed. The structure of the power combiner already developed are Branch-line coupler, Rat-race coupler, Wilkinson coupler, Lange coupler, etc. Which are all planar, If the frequency goes up, the coupling efficiency of these planar couplers is decreased on account of skin loss. Especially, in millimeter-wave band, the efficiency of more than two ways combiner is radically reduced, so that application in power amplifier circuit is almost impossible, Microstrip-slotline transition structure is a power combining technique integrated into wave-guide, so that the loss is small and the efficiency is high. Theoretically, we can mount several transistors into the power-combiner. This makes it possible to develop a high power amplifier. The numerically calculated performances of the device that is, we believe, the best are compared to the experimental results in Ka-Band(26.5GHz-40GHz).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.10 no.1
• /
• pp.90-98
• /
• 1999

This paper presents a wideband single-balanced mixer using a diode which can be used in RF receiver of microwave measurement systems. For wideband characteristic, local oscillator(LO) signal is provided to diode with low loss using a coplanar waveguide-to-slotline balun. For high isolation characteristic radio frequency (RF) port and intermediate frequency (IF) port are designed using directional coupler. This mixer presents 30.5~31.17dB conversion loss whose flatness is within 1dB for 9 kHz~2.6 GHz wideband RF signal, and above 30 dB isolation for LO signal.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.345-348
• /
• 1999

본 논문에서는 내장형 응용에 적합한 RISC 마이크로프로세서와 DSP 프로세서의 기능을 유기적으로 결합한 구조를 연구하고 이를 설계한다. 프로그램의 크기를 줄이기 위해 RISC 명령어는 16비트 명령어 집합을 설계하고 분기 명령어로 인한 손실을 줄이기 위해 한 개의 지연 슬롯을 갖고 있다. DSP 명령어는 32비트 길이를 갖고 한 명령어로 곱셈, 덧셈(뺄셈), 두 가지 데이터 이동을 할 수 있어서 한 사이클에 최대 네 가지 동작을 할 수 있다 파이프라인 단계는 IF, ID, EX, MA, WB/DSP의 다섯 단계로 구성된다. DSP 기능을 지원하기 위해 내부 루프 버퍼를 갖고 정수 실행부에서는 주소 발생을 위한 전용 하드웨어와 DSP 유닛에서는 곱셈 및 누적 기능을 지원하기 위한 17 × 17 비트 곱셈기가 내장된다. 제안된 구조의 설계는 Verilog-HDL을 이용하여 top-down 설계 방식으로 설계되었고 각 기능 검증을 마친 후 3.3V, 0.6㎛ CMOS triple metal single poly 공정을 이용하여 합성하고 레이아웃 하였다.