• Title/Summary/Keyword: 스트리밍 멀티프로세서

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A Study on the Security Processor Design based on Pseudo-Random Number in Web Streaming Environment

  • Lee, Seon-Keun
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.6
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    • pp.73-79
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    • 2020
  • Nowadays, with the rapid spread of streaming services in the internet world, security vulnerabilities are also increasing rapidly. For streaming security, this paper proposes a PN(pseudo-random noise) distributed structure-based security processor for web streaming contents(SP-WSC). The proposed SP-WSC is basically a PN distributed code algorithm designed for web streaming characteristics, so it can secure various multimedia contents. The proposed SP-WSC is independent of the security vulnerability of the web server. Therefore, SP-WSC can work regardless of the vulnerability of the web server. That is, the SP-WSC protects the multimedia contents by increasing the defense against external unauthorized signals. Incidentally it also suggests way to reduce buffering due to traffic overload.

A General Purpose DSP based Multimedia Streaming System (General Purpose DSP 기반의 멀티미디어 스트리밍 시스템 구현)

  • Kim, Dong-Hwan;Moon, Jae-Pil;Oh, Hwa-Yong;Lee, Eun-Seo;Chang, Tae-Gyu
    • Proceedings of the KIEE Conference
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    • 2005.07d
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    • pp.2882-2884
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    • 2005
  • 본 논문에서는 인터넷을 통한 멀티미디어 스트리밍 서비스 환경에서 다양한 표준으로 압축된 컨텐츠의 디코딩을 지원하기 위하여 general purpose DSP (Digital Signal Processor) 기반의 멀티미디어 서비스 플랫폼을 구현하였다. 다양한 표준 방식으로 압축된 멀티미디어 컨텐츠를 재생하기 위하여 Host 프로세서와 DSP 구조의 하드웨어를 설계하고, 멀티미디어 코덱을 DSP에 다운로드하는 소프트웨어적인 기법을 적용하였다. 설계한 플랫폼의 동작을 검증하기 위하여 리눅스 기반에서 DSP를 제어하는 네트워크 클라이언트 소프트웨어를 구현하고, Tl의 TMS 320C6416을 대상으로 구현한 MPEG-2 비디오와 AC-3 오디오 코덱을 적용하여 스트리밍 환경에서 멀티미디어 데이터가 원활하게 재생되는 것을 보였다.

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A Real-Time Scheduling Technique on Multi-Core Systems for Multimedia Multi-Streaming (다중 멀티미디어 스트리밍을 위한 멀티코어 시스템 기반의 실시간 스케줄링 기법)

  • Park, Sang-Soo
    • Journal of Korea Multimedia Society
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    • v.14 no.11
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    • pp.1478-1490
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    • 2011
  • Recently, multi-core processors have been drawing significant interest from the embedded systems research and industry communities due mainly to their potential for achieving high performance and fault-tolerance at low cost in such products as automobiles and cell phones. To process multimedia data, a scheduling algorithm is required to meet timing constraints of periodic tasks in the system. Though Pfair scheduling algorithm can meet all the timing constraints while achieving 100% utilization on multi-core based system theoretically, however, the algorithm incurs high scheduling overheads including frequent core migrations and system-wide synchronizations. To mitigate the problems, we propose a real-time scheduling algorithm for multi-core based system so that system-wide scheduling is performed only when it is absolutely necessary. Otherwise the proposed algorithm performs scheduling within each core independently. The experimental results by extensive simulations show that the proposed algorithm dramatically reduces the scheduling overheads up to as negligible one when the utilization is under 80%.

Implementation of A Low-Power Embedded System via Scratch-pad Memory Compression (스크래치 패드 메모리의 압축을 통한 저전력 임베디드 시스템의 구현)

  • Suh, Hyo-Joong
    • The KIPS Transactions:PartA
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    • v.15A no.5
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    • pp.269-274
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    • 2008
  • Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

Embracing Device Characteristics for Dynamic Adaptive Video Streaming (DLNA 기기 특성을 고려한 동적 적응형 스트리밍에 대한 연구)

  • Kim, Mijung;Jin, Feng;Yoon, Ilchul;Jin, Xianshu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.574-577
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    • 2014
  • Multimedia contents sharing services based on DLNA (Digital Living Network Alliance) technology such as Allshare or Smartshare in wireless home networks is widely adapted in Korea. However, the characteristics of the wireless network - frequently fluctuated bandwidth and signal strength could degrade the quality perceived by users. To minimize the impact of the challenge there are active researches in dynamic adaptive streaming. This paper proposes a dynamic adaptive streaming approach designed in a wireless network taking into account of the specifications of the user device such as resolution and processor. We modify the Kalman filter considering the characteristics of the device and demonstrate that the proposed approach determines Bit Rate using the modified filter.

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A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization (GPGPU 자원 활용 개선을 위한 블록 지연시간 기반 워프 스케줄링 기법)

  • Thuan, Do Cong;Choi, Yong;Kim, Jong Myon;Kim, Cheol Hong
    • KIPS Transactions on Computer and Communication Systems
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    • v.6 no.5
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    • pp.219-230
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    • 2017
  • General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.

Design for MOST network device on AVR32 processor (AVR32 프로세서를 이용한 MOST 네트워크 장치 설계)

  • Park, Duck-Keun;Jeong, Sung-Hwan;Lee, Sang-Yub;Choi, Hyo-Sub;Lee, Chul-Dong
    • Proceedings of the Korea Information Processing Society Conference
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    • 2012.11a
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    • pp.27-28
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    • 2012
  • 오늘날 차량 기술에 대한 관심사는 기계적 성능에서 각종 전자장치를 사용한 기술로 이동하고 있다. 특히 자동차 내에서 각종 멀티미디어 서비스 및 여러 정보들의 통합 분석을 위해서 자동차 네트워크 기술이 각광받고 있다. 본 논문에서는 자동차 네트워크 기술 중 MOST(Media Oriented System Transport)네트워크를 사용하기 위한 장치로 저가형 장치인 MiniAMG 단말기를 제안한다. Mini AMG 단말기를 통해 어떻게 오디오 스트리밍 서비스를 제공하는지와 향후 어떠한 방향으로 사용 가능한지에 대해 기술하였다.

A Hardware Cache Prefetching Scheme for Multimedia Data with Intermittently Irregular Strides (단속적(斷續的) 불규칙 주소간격을 갖는 멀티미디어 데이타를 위한 하드웨어 캐시 선인출 방법)

  • Chon Young-Suk;Moon Hyun-Ju;Jeon Joongnam;Kim Sukil
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.658-672
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    • 2004
  • Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

The Study on Development of a Digital Internet Radio Receiver (디지털 인터넷 라디오 수신기 구현에 대한 연구)

  • Park, In-Gyu
    • Journal of KIISE:Computing Practices and Letters
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    • v.12 no.2
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    • pp.102-110
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    • 2006
  • This paper explains the design and development of the stand-alone high sound quality Internet Radio system, which is aimed for a small embedded type audio device rather than a general PC type. This device is designed to work with an Internet connection. This kind of system is not standardized so far, and also the related algorithm is not open to the public. So it is necessary to analyze several receiving algorithms of current radio receivers, and develop our own hardware in order to overcome these obstacles, finally to get the high quality of sound radio. The main electronic components of this Internet Radio are TCP/IP interfaces, an audio MP3 decoder, an I/O interface, and a Flash Memory Card with advanced audio multicasting for the next-generation Internet Radio. Basic structures and implementation issues of the next-generation most-versatile digital music player, and Internet Radio receivers, are discussed.

Collaborative Streamlined On-Chip Software Architecture on Heterogenous Multi-Cores for Low-Power Reactive Control in Automotive Embedded Processors (차량용 임베디드 프로세서에서 저전력 반응적 제어를 위한 이기종 멀티코어 협력적 스트리밍 온-칩 소프트웨어 구조)

  • Jisu, Kwon;Daejin, Park
    • IEMEK Journal of Embedded Systems and Applications
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    • v.17 no.6
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    • pp.375-382
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    • 2022
  • This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.