• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2107-2115
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• 2007

In this paper, the scan conversion processor which converts the triangle represented by three vertices into pixel-level screen coordinates, depth coordinate, and color data is designed. The processor adopts scan-line algorithm which decomposes triangle into horizontal spans and then transforms the span into pixel data. By supporting top-left filling convention, it ensures that triangles that share an edge do not produce any dropouts or overlaps between adjacent polygons. It consists of about 21,400 gates and its maximum operating frequency is about 80 Mhz under 0.35um CMOS technology. Because its maximum pixel rate is about 80 Mpixels/sec, it can be applicable to mobile graphics application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2023-2030
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• 2010

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.7-9
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• 2001

ASIC 설계에서 gated clock으로 동작하는 clock을 입력으로 받는 회로들은 스캔 테스트를 수행하기에 용이하지 않다. 이러한 회로들에 대하여 스캔 테스트기법을 적용하기 위한 설계변경기술을 제안한다. 제안하는 설계변경기술은 비동기 회로를 동기 회로로 변환함으로써 스캔 기법을 적용할 수 있는 회로로 변환하게 된다. 이로써 테스트를 좀 더 용이하게 수행할 수 있을 뿐 아니라 결함 시험도를 높이게 되는 효과를 가져올 수 있다.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.288-296
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• 2003

ATSC (Advanced Television System Committee) has specified 18 video formats for DTV (Digital Television), e.g., scan format, size format, and frame rate format conversion. Effective MPEG-2 video transcoders should support any conversion between the above-mentioned formats. Scan format conversion Is hard to Implement because it may often induce frame rate and size format conversion together. Especially. because of picture type conversion caused by scan format conversion, the computational burden of motion estimation (ME) in transcoding becomes serious. This paper proposes a fast ME algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MVs) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MVs by using a weighted median selector. Simulation results show that the proposed ME algorithm provides outstanding PSNR performance close to full search ME, while reducing the transcoding complexity significantly.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.855-858
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• 1998

본 연구에서는 MML(merged memory logic)구조를 갖는 스캔라인 컨버터를 설계하여 제안한다. 비월주사 방식인 TV 비디오 신호를 FIFO 메모리에 저장하여 순차주사방식인 VGA 비디오 시모호 변환하는 주사선 변환기를 MML 개념으로 설계하였다. MML 회로는 VHDL로 설계하여 V-system으로 시뮬레이션을 수행하고 altera FPGA에 구현한 후, TV 비디오 신호를 PC 모니터로 보기 위한 외장형 tV 수신 시스템에 적용하여 성능을 검증했다. MML 개념으로 설계된 컨버터는 system-on-a-chip 설계의 첫 단계로 메모리와 로직부분으로 구성된 일반적인 컨버터보다 효율적인 시스템 설계를 할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.4
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• pp.87-87
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• 2001

일반화 대칭 변환 (generalized symmetry transform, GST)은 주어진 영상에서 사전 분할이 없이 국부성과 반사 대칭성을 결합하여 대칭을 측정하고 관심 영역을 추출한다. GST의 거리 가중치 함수에서 국부적인 대칭성이 반영되며 이 함수의 표준 편차 u에 의해 GST의 수행 범위가 조절된다. 넓은 관심영역을 추출하기 위해 반지름 r이 큰 검색영역 내에서의 대칭성이 추출될 필요가 있다. 이에 따라서 GST의 수행시간은 r에 따라 2차적으로 증가하게 된 본 논문에서는 이를 개선하기 위해 선택적 방향 주의를 가지는 수정된 스캔라인 GST를 제안한다. 제안된 GST는 기존의 GST와 유사한 대칭 특성을 추출하지만 선택적 방향의 기울기만을 고려한 스캔라인 위의 에지 화소쌍에서 GST를 수행함으로써 r에 따라서 이의 수행시간이 선형적으로 증가된다 특히 r이 큰 경우에 선택적 방향에 대해서만 적용하면 기존의 GST의 계산량이 비대해지는 단점을 보완해 줄 수 있다. 제안된 GST가 기존의 GST보다 시간적으로 효과적이며 유용하다는 것이 여러 종류의 영상에 대한 실험으로 확인되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.3
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• pp.504-514
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• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.320-325
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• 2006

An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.4
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• pp.69-74
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• 2004

In this paper, we propose a novel method for improving defect-detection performance based on reconstruction of line-scan camera images using both the projection profiles and color space transform. The proposed method consists of RGB region segmentation, representative value reconstruction using the tracing system, and Y image reconstruction using color-space transformation. Through experiments it is demonstrated that the performance using the reconstructed image is better than that using aerial image for LCD surface inspection.