• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Journal of the Korean Society of Marine Environment & Safety
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• v.13 no.4
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• pp.21-26
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• 2007

A study on analysis and application of ocean currents information extracted from SAR (Synthetic Aperture Radar) satellite image. The current information extracted from SAR satellite image is not real vector information but scalar information in normal direction of orbital path. To correct current information extracted from satellite image, observation of currents in the field is carried out at the same time and area as those of satellite image. In the analysis, current information extracted from satellite image is corrected by using observed ones. By this correction, the speed and the direction of current can be estimated. The extract current information seem to agree well with the observed ones.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.445-448
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• 2005

A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.

• Journal of the Korea Concrete Institute
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• v.17 no.4 s.88
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• pp.513-520
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• 2005

The uniform truss mechanism is widely accepted as a shear transfer mechanism in reinforced concrete members. However, the uniform truss action cannot be expected when the bond stress distribution is not constant along longitudinal bars. A test method in which only the truss action takes place is developed and conducted to investigate the truss actions under various bond contributions. Based on the experimental results and analysis, the following findings can be obtained: 1) The bond stress distribution depends on the axial compression force, the amount of shear reinforcement and loading conditions. 2) The analysis using the combined truss model consisting of uniform and fan-shape trusses can predict the experimental results

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1155-1163
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• 2011

In this paper, we propose a new pre-processing algorithm applied to depth map to improve the coding efficiency. Now, 3DV/FTV group in the MPEG is working for standard of 3DVC(3D video coding), but compression method for depth map images are not confirmed yet. In the proposed algorithm, after dividing the histogram distribution of a given depth map by EM clustering method based on GMM, we classify the depth map into several layered images. Then, we apply different mean shift filter to each classified image according to the existence of background or foreground in it. In other words, we try to maximize the coding efficiency while keeping the boundary of each object and taking average operation toward inner field of the boundary. The experiments are performed with many test images and the results show that the proposed algorithm achieves bits reduction of 19% ~ 20% and computation time is also reduced.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• The Journal of the Acoustical Society of Korea
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• v.25 no.3
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• pp.113-120
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• 2006

This paper is concerned with a equalization technique for Orthogonal Frequency Division Multiplexing (OFDM) systems based on a block type pilot arrangement over slow fading channels. The bit rates obtained in underwater channels are relatively modest compared to some other communication channels such as cellular phones or indoor wireless systems. Consequently. the Doppler effect is the important parameter in tracking a channel. In case of a coherent demodulation scheme, the residual mean phase errors due to Doppler frequency may be fatal for the performance of the system. The equalizer could not solely handle mean Doppler shift. To account for the common Doppler effect a phase error tracking loop is used with the frequency equalizer. so that the rotation errors are avoided. Furthermore. simulations show that we can reduce the computational load of the tracking loop with negligible effect on performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.1
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• pp.12-18
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• 1978

From the state table of sequential machines, Roomers) obtained minimal k co-mapping chain(k-CC) and proposed an algorithm obtaining binary partitions which were seed partitions of S-shift registers. By comparing and processing bits simply, this paper obtained two different algorithms more efficient than that of Roome's for obtaining such binary partitions and defined the concept of the triple pair of the basis partitions. By using the concept, given set of basis partitions was reduced to the set containing elements of the triple pair only and the algorithm became quite simple.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.667-670
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• 2005

본 논문은 100um와 80um의 텅스텐 와이어를 이용하여 세라믹(Ceramic)기판에 홀(Hole)을 뚫어 텅스텐 와이어를 수직으로 세우는 방식으로 수직형의 마이크로 스프링을 제작하였다. 마이크로 스프링의 설계를 위해 제한된 실험 결과와 신경회로망을 이용하여 텅스텐 와이어의 두께와 높이, 쉬프트(Shift)의 양을 변화시키면서 장력(Tension force)을 모델링하였고 제작을 통해 검증하였다. 이는 기존의 수평형 프로브카드의 한계를 대체할 수 있는 수직형 프로브카드의 핵심 모듈로서 멀티다이(Multi Die) 뿐만 아니라 범핑(Bumping)타입의 칩 테스트도 가능하다.