• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.157-165
• /
• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.106-114
• /
• 2016

In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.3
• /
• pp.49-59
• /
• 2002

As the electronic commerce increases rapidly in the mobile communication, security issues become more important. A suitable authentication and key agreement for the mobile communication environment is a essential condition. Some protocols based on the public key cryptosystem such as Diffie-Hellman, EIGamal etc. were adapted in the mobile communication. But these protocols that are based on the difficult mathematical problem in the algebra, are so slow and have long key-length. Therefore, these have many limitation to apply to the mobile communication. In this paper, we propose an authentication and key agreement protocol based on NTRU to overcome the restriction of the mobile communication environment such as limited sources. low computational fewer, and narrow bandwidth. The proposed protocol is faster than other protocols based on ECC, because of addition and shift operation with small numbers in the truncated polynomial ring. And it is as secure as other existent mathematical problem because it is based on finding the Shortest or Closest Vector Problem(SVP/CVP).

• Journal of Broadcast Engineering
• /
• v.1 no.2
• /
• pp.108-117
• /
• 1996

In this paper we propose a Wavelet- based compression algorithm of HDTV video signals for the purpose of recording HDTV signals in the digital VTR. Comparing to the DCT- based compression method, which only yields unrecognizable DCT coefficients, the low frequency components of Wavelet coefficients maintain recognizable spatial domain information. So, it is more suitable for various VTR operations such as editing and multi-speed mode operations. Also, the adopted Wavelet filter can be Implemented with simple shift operations, which can reduce the computational complexities substantially. The quality of reconstructed HDTV signals with a 4:1 compression ratio turns out to be good enough for the studio use.

• The Journal of the Korea Contents Association
• /
• v.14 no.3
• /
• pp.11-21
• /
• 2014

Multi-scale image segmentation is important in many applications such as image stylization and medical diagnosis. This paper proposes a novel segmentation algorithm based on MSER(maximally stable extremal region) which captures multi-scale structure and is stable and efficient. The algorithm collects MSERs and then partitions the image plane by redrawing MSERs in specific order. To denoise and smooth the region boundaries, hierarchical morphological operations are developed. To illustrate effectiveness of the algorithm's multi-scale structure, effects of various types of LOD control are shown for image stylization. The proposed technique achieves this without time-consuming multi-level Gaussian smoothing. The comparisons of segmentation quality and timing efficiency with mean shift-based Edison system are presented.

• Smart Media Journal
• /
• v.3 no.1
• /
• pp.39-45
• /
• 2014

The partial product matrix of a parallel squarer are symmetric about the diagonal. To reduce the number of partial product bits and the depth of partial product matrix, it can be typically folded, shifted and bit-rearranged. In this paper, an efficient design approach for the combined squarer, capable of operating on either unsigned or signed numbers based on a mode selection signal, is presented. By simulations, it is shown that the proposed combined squarers lead to up to 18% reduction in area, 11% reduction in propagation delay and 9% reduction in power consumption compared with the previous combined squarers.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.12
• /
• pp.77-84
• /
• 2005

The orthogonal frequency division multiplexing (OFDM) technique and the single carrier with cyclic prefix (SC-CP) scheme are very attractive solutions for wireless applications, being computationally efficient since equalization is performed in the frequency domain. The equalizer could not entirely handle significant mean. Doppler shift. This motivates the use of a phase error tracking loop that operates jointly with the frequency equalizer. This paper describes the effect of the mean phase error and the performance of the proportional equalizer coupled with a phase error tracking loop based on decision-directed method. Furthermore, simulation results show that we can reduce the computational toad of the tracking loop with minimal performance degradation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.271-274
• /
• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.65-70
• /
• 2008

In FIR filter design, multipliers occupy most of the area. To efficiently reduce the area occupied by multipliers, Common Subexpression Elimination (CSE) algorithm can be used instead of separate multipliers. However, the filter computation time can be increased due to the long carry propagation in CSE circuits. More specifically, when the difference of weights between the two inputs to an adder in CSE circuits is large, long carry propagation time is required due to large sign extension. In this paper, we propose a sign-extension reduction method in common subexpression elimination circuit. By Synopsys simulation using Samsung 0.35um library, it is shown that the proposed method leads to 17%, 31% and 12% reduction in the area, time delay and power consumption, respectively, compared with conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.12
• /
• pp.1062-1070
• /
• 2002

In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.