• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.197-201
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• 2007

The accelerated aging test equipment which is possible to apply voltage and temperature at the same time, is fabricated to predict lifetime of high capacity thyristor in short time. The variations of the forward/reverse breakdown voltage and the leakage current are investigated as an aging diagnostic tool. Lifetimes of the devices which are predicted from the reverse breakdown voltage with an accelerated aging time, have shown 3-15 years.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.172-175
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• 2005

a-Si TFT는 TFT-LCD의 화소 스위칭(swiching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압의 이동이다. 펄스(pulse)형태로 인가되는 gate 전압에 의한 문턱 전압 이동은 a-Si:H gate에 인가되는 펄스의 크기, duty cycle, drain pulse의 크기 및 동작 온도에 기인하며 실험결과를 통해 입증된다. 초기의 DC Stress 측정 Data를 이용하여 문턱전압이동을 모델링/시뮬레이션한 결과 a-Si:H gate 회로설계 및 펄스 조건에 따라 stress시간에 따른 gate의 출력 파형 예측이 가능하고 상온에서 Von=21V를 인가한 결과, 약 4년후에서 시프트레지스터 출력 파형이 열화되기 시작한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.315-316
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• 2005

This paper describes the AC accelerated ageing characteristics of zinc oxide varistors for the station class lightning surge arresters. ZnO varistors whose rated voltage were 3.27kV, 4.00kV, and 6.00kV were manufactured with general ceramic production methods. The power loss of sample A varistors rapidly increased and eventually showing the thermal run-away, but sample B and sample C varistors exhibited negative creep phenomena in power losses during the test.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.51-54
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• 1996

This paper reports the studies of the inversion layer mobility in p-channel Si MOSFET's under hot-carrier degradated condition. The validity of relationship of hot carrier degradations between the surface effective mobility and field effect mobility and are examined. The effective mobility(${\mu}$$\_$eff/) is derived from the channel conductances, while the field-effect mobility(${\mu}$$\_$FE/) is obtained from the transconductance. The characteristics of mobility curves can be divided into the 3 parts of curves. It was reported that the mobility degradation is due to phonon scattering, coulombic scattering and surface roughness. We are measured the mobility slope in curves with DC-stress [V$\_$g/=-3.1v]. It was found that the mobility(${\mu}$$\_$eff/ and ${\mu}$$\_$FE/) of p-MOSFET's was increased by increasing stress time and decreasing channel length. Because of the increasing stress time and increasing V$\_$g/ is changed oxide reliability and increased vertical field.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.59-64
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• 1994

The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.05a
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• pp.110-110
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• 2009

최근 차세대 비휘발성 메모리(NVM) 기술은 메모리의 성능과 기존의 한계점을 효과적으로 극복하며 활발한 연구를 통해 비약적으로 발전하고 있으며 특히, phase-change random access memory (PRAM)은 ferroelectric random access memory (FeRAM)과 magneto-resistive random access memory (MRAM)과 같은 다른 NVM 소자와 비교하여 기존의 DRAM과 구조적으로 비슷하고 상용화가 빠르게 진행될 수 있을 것으로 예상되는 바, PRAM에 사용되는 상변화 물질의 식각을 수행하고 X-ray photoelectron spectroscopy (XPS)를 통해 표면의 열화현상을 관찰하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1740-1742
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• 1998

This paper describes the technique of deterioration diagnosis for ZnO element. Due to the non-linear resistance of ZnO block, the total leakage current contains harmonics when arrester deteriorated. The most significant harmonics is the 3rd order component. So, it can be used as an indicator of the arrester condition. An iron core, which has a very high relative permeability, is used for increasing detection sensitivity and the 3th order harmonics of leakage current was detected by band-pass circuit. And we have verified the reliability and performance of the sensing device through several laboratory tests.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.311-312
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• 2008

$RuO_2$ 계열의 후막재료를 사용한 저항의 신뢰성시험을 실시하고 주요 고장 메커니즘을 확인하였다. 사용된 소자의 기판은 AlN 세라믹 기판이며, 후막재료로 $RuO_2$ paste를 프린팅하고 소결시킨 구조의 고주파용 저항(RF Termination)이다. 주요 고장 메커니즘은 후막(Thick Film)의 특성변화, 기판의 특성변화, 전극-후막 간의 접촉특성변화, Trimming 부위의 열화, 열팽창계수 차이에 의한 기계적 파손 등으로 알려져 있으며, 본 실험에서는 고장모드 분석을 위해 과부하시험, 고온동작시험 등을 포함한 신뢰성 환경시험과 수명시험을 실시하였다. 각 시험 결과 수명시험 후 전극-후막 간의 접합부 파괴가 관찰되었고, 열충격 시험 결과 후막의 crack이 관찰되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.356-357
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• 2008

The effects of $O_2$ plasma ashing process for surface treatment of nano-wire Bio-FET were investigated. In order to evaluate the plasma damage introduced by $O_2$ plasma ashing, a back-gate biasing method was developed and the electrical characteristics as a function of $O_2$ plasma power were measured. Serious degradations of electrical characteristics of nano-wire Bio-FET were observed when the plasma power is higher than 50 W. For curing the plasma damages, a forming gas anneal (2 %, $H_2/N_2$) was carried out at $400^{\circ}C$. As a result, the electrical characteristics of nano-wire Bio-FET were considerably recovered.