• The Journal of the Korea Contents Association
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• v.17 no.9
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• pp.437-448
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• 2017

This study was conducted as a qualitative case study for examining what transformed primary concepts and transformed schemas were formed for the addition of decimals and how they were formed, and how the relational understanding of the addition of decimals was in three 3rd grade elementary school children who had studied the primary concepts of division, fraction and decimal. That is, this study investigated how the subjects approached problems of decimal addition using transformed primary concepts and transformed schemas formed by themselves, and how the subjects formed concepts and transformed schemas in problem solving. According to the results of this study, transformed primary concepts and transformed schemas formed through the learning of the primary concepts of division, fraction, and decimal functioned as important factors for the relational understanding of decimal addition.

• Education of Primary School Mathematics
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• v.14 no.3
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• pp.317-328
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• 2011

We analyzed errors committed by Korean prospective elementary teachers in finding and interpreting quotient and remainder within measurement division of fractions. 65 prospective elementary teachers were participated in this study. They solved a word problem about measurement division of fractions. We analyzed solutions of all participants, and interviewed 5 participants of them. The results reveal many of these prospective teachers could not tell what fractional part of division result means. Thses results suggest that teacher preparation program should emphasize interpreting calculation results within given situations.

• Education of Primary School Mathematics
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• v.21 no.3
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• pp.309-327
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• 2018

This study is a case study of an elementary school teacher's reflection and practice in the process of planning, executing and criticizing his lesson on division with decimals. The purpose of this study was to clarify what kinds of problems an elementary school teacher was thinking about and how his focus was changing in the process of planning and executing a lesson and criticizing his lesson with his peers. The teacher was set in three periods: a teacher planning a lesson, a teacher executing a lesson, and a teacher criticizing his or her own lesson. Each period was analyzed in eight aspects: Establishing the goals for mathematics, implementing tasks, connecting mathematical representations, facilitating mathematical discourse, posing questions, building procedural fluency from conceptual understanding, supporting productive struggles, and using evidences of students' thinking.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.119-122
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• 2001

본 논문에서는 음성압축 앨고리즘인 MPEG-4 CELP coder를 16 bit DSP 구현에 필요한 고정소수점 연산구조로 구현하였다. 기본 앨고리즘 중에 LSP 계수를 구하는 방법인 Chebyshev series method 대신 고정소수점 구현에 유리한 Real root method 앨고리즘을 사용하였다. 또한 cosine, log 둥 DSP 명령어가 지원하지 않는 수학 함수들은 미리 계산하여 테이블 적용기법을 사용하였고 고정 소수점 연산에 불리한 나눗셈 연산을 최대한 배제하였다. 고정 소수점 연산 구조로 변환한 후 부동 소수점 연산구조와의 비교를 통하여 오차를 최소화하도록 하였다 구현한 음성코더를 남, 여 각 5문장에 적용했을 때 부동 소수점 연산구조에 비교해 음질의 열화가 없음을 확인하였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.123-129
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• 2013

The performance and practicality of cryptosystem for encryption, decryption, and primality test are primarily determined by the implementation efficiency of the modular exponentiation of $a^b$ (mod m). To compute $a^b$ (mod m), the standard binary squaring (square-and-multiply) still seems to be the best choice. However, in large b bits, the preprocessed n-ary, ($n{\geq}2$ method could be more efficient than binary squaring method. This paper proposes a square-and-divide and unpreprocessed n-ary square-and-divide modular exponentiation method. Results confirmed that the square-and-divide method is the most efficient of trial number in a case where the value of b is adjacent to $2^k+2^{k-1}$ or to. $2^{k+1}$. It was also proved that for b out of the beforementioned range, the unpreprocessed n-ary square-and-divide method yields higher efficiency of trial number than the general preprocessed n-ary method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of the Korean School Mathematics Society
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• v.11 no.2
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• pp.285-298
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• 2008

According to the 7th curriculum, irrational numbers should be introduced using infinite decimals in 9th grade. To do so, the relation between rational numbers and decimals should be explained in 8th grade. Preceding studies remarked that middle school students could understand the relation between rational numbers and decimals through the division appropriately. From the point of view with the arithmetic handling activity, I analyzed that the integers and terminating decimals was explained as decimals with repeating 0s or 9s. And, I reviewed the equivalent relations between irrational numbers and non-repeating decimals, rational numbers and repeating decimals. Furthermore, I suggested an alternative method of introducing irrational numbers.

• School Mathematics
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• v.14 no.1
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• pp.45-64
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• 2012

The purpose of the present study was to investigate middle grades (Grade 5-7) mathematics teachers' knowledge of partitive fraction division. The data were derived from a part of 40-hour professional development course on fractions, decimals, and proportions with 13 in-service teachers. In this study, I attempted to develop a model of teachers' way of knowing partitive fraction division in terms of two knowledge components: knowledge of units and partitioning operations. As a result, teachers' capacities to deal with a sharing division problem situation where the dividend and the divisor were relatively prime differed with regard to the two components. Teachers who reasoned with only two levels of units were limited in that the two-level structure they used did not show how much of one unit one person would get whereas teachers with three levels of units indicated more flexibilities in solving processes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.187-193
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• 2020

Floating point arithmetic in microprocessor is the computation of addition, subtraction, multiplication, and division of floating point data to improve accuracy. In general, when designing a processor, floating point instructions are often excluded because of its complexity and only integer instructions are provided. However, in order to carry out the computations for not only engineering and technical operations but also artificial intelligence and neural networks that are in the spotlight today, floating point operations must be included. In this paper, we design a 32-bit ARMv4 family of processors with floating-point arithmetic instructions using VHDL and verify with ModelSim. As a result, ARM's floating point instructions are successfully executed.