• Title/Summary/Keyword: 소모

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Development of Bicyclists' Route Choice Model Considering Slope Gradient (경사도 에너지 소모량을 고려한 자전거 경로 선택 모형 개발)

  • Lee, Kyu-Jin;Ryu, Ingon
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.19 no.3
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    • pp.62-74
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    • 2020
  • Although the government and local governments devote efforts to activate bicycles, they only access to the supply infrastructure such as bike lanes and the public bicycle rental service centers without considering the measures to overcome the geographical constraints of slope. Therefore, this study constructs bicyclist's energy consumption estimation model through experimental methods of slope gradient and heart rate measurement and suggest the bicycle route choice model which could minimize the energy by the slope gradient. After calculating the RMSE of the estimated energy consumption by applying this model to the simulation section, it is confirmed to be 41% better than the model which does not reflect slope gradient. The results of this study are expected to be applied to the bicycle infrastructure planning that considers both longitude and transverse of bike lanes and the algorithm of bicycle route guidance system in the future.

Energy Consumption of Taekwondo Practitioners due to a Thigh Muscle Extracted by CT Scan (CT Scan으로 추출한 허벅지 근육량에 따른 태권도 수련자의 에너지 소모량)

  • Kim, Changmo;Ha, Insuk;Lee, SangBock
    • Journal of the Korean Society of Radiology
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    • v.7 no.3
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    • pp.199-204
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    • 2013
  • Despite the suzerain of Korea Taekwondo physical activity and a corresponding lack of basic research on energy consumption and the status of this research is urgent. In this study, the sensor (SenseWear (R) PRO2 Armband), using physical activity were obtained in Taekwondo, and body composition data were obtained by Inbody 520, We were thigh scan using CT scanner and thigh muscle area by CT scan data were acquired. Result of analysis, average thigh muscle area of experimenter 8 people was 132.79 $cm^2$, Of 20 cm above the patella thigh was a 178.79 $cm^2$. Thigh circumference and muscle area showed that the correlation. The average energy consumption per minute was 6.94 calories, and thigh muscle area and average energy consumption per minute also showed that correlation.

An Optimized Sleep Mode for Saving Battery Consumption of a Mobile Node in IEEE 802.16e Networks (IEEE 802.16e 시스템에서 이동 단말의 전력 소모 최소화를 위한 취적 휴면 기법)

  • Park, Jae-Sung;Kim, Beom-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3A
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    • pp.221-229
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    • 2007
  • In this paper, we propose and analyze the optimized sleep mode for a mobile node (MN) in IEEE 802.16e wireless metropolitan area networks. Because a MN in a sleep mode specified in 802.16e specification should maintain state information with the base station currently attached, it must renew sleep state with a new base station after handover which leads to unnecessary waste of battery power. Noting that the mobility pattern of a MN is independent of call arrival patterns, we propose an optimized sleep mode to eliminate unnecessary standby period of a MN in sleep state after handover. We also propose an analytical model for the proposed scheme in terms of power consumption and the initial call response time. Simulation studies that compare the performance between the sleep mode and the optimized sleep mode show that our scheme marginally increases initial call response delay with the huge reduction in power consumption.

A Low Power ROM Using A Single Charge Sharing Capacitor and Hierarchical Bit Line (한 개의 전하공유 커패시터와 계층적 비트라인을 이용한 저전력 롬)

  • Yang, Byung-Do
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.76-83
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    • 2007
  • This paper describes a low power ROM using single charge-sharing capacitor and hierarchical bit line (SCSC-ROM). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a very small voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and make easy to design. The hierarchical bit line further saves the power by reducing the capacitance in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with $4K{\times}32bits$consumes only 37% power of a conventional ROM. A SCSC-ROM chip is fabricated in a $0.25{\mu}m$ CMOS process. It consumes 8.2mW at 240MHz with 2.5V.

A Low Power Algorithm using State Transition Ready Method (상태 전환 준비 방법을 이용한 저전력 알고리즘)

  • Youn, Choong-Mo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.9
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    • pp.971-976
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    • 2014
  • In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

A Study on Battery Driven Low Power Algorithm in Mobile Device (이동기기에서 배터리를 고려한 저전력 알고리즘 연구)

  • Kim, Jae-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.2
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    • pp.193-199
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    • 2011
  • In this paper, we proposed battery driven low power algorithm in mobile device. Algorithm the mobile devices in power of the battery for the task to perform power consumption to reduce the frequency alters. Power of the battery perform to a task power consumption of is less than the task perform to frequency the lower. Frequency control the task, depending on in the entire system devices used among the highest frequency with devices first target perform to. Frequency in the decrease the second largest frequency with of the device the frequency in changes the power consumption to calculate. The calculated consumption power the battery of level is greater than level the frequency by adjusting power consumption, lower power of the battery the task perform when you can to the frequency to adjust. Experiment the frequency by adjusting power consumption a method to reduce using [6] and in the same environment power of the battery consider the task to perform frequency were controlled. The results in [6] perform does not battery power on task operates that the result was.

Energy-Aware Task Scheduling for Multiprocessors using Dynamic Voltage Scaling and Power Shutdown (멀티프로세서상의 에너지 소모를 고려한 동적 전압 스케일링 및 전력 셧다운을 이용한 태스크 스케줄링)

  • Kim, Hyun-Jin;Hong, Hye-Jeong;Kim, Hong-Sik;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.22-28
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    • 2009
  • As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

Manufacturing of Methane Hydrate using THF-Carbon Nanotube Nanofluids (THF-탄소나노튜브 나노유체를 이용한 메탄 하이드레이트 제조)

  • Park, SungSeek;An, EoungJin;Kim, NamJin
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.11a
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    • pp.123.1-123.1
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    • 2011
  • 본 연구에서는 THF(Tetrahydrofuran)와 산화탄소나노튜브를 혼합한 유체가 메탄 하이드레이트 생성에 어떠한 영향을 미치는지 알아보기 위해 하이드레이트 생성실험을 수행하고 비교분석하였다. 먼저 하이드레이트 생성 시 정확히 큰 동공에 하나의 THF 분자를 위치시킬 수 있는 5.56 mol%의 THF 혼합유체와 0.003 wt%의 산화 탄소나노튜브를 첨가한 산화탄소나노유체에서 하이드레이트 생성실험을 수행한 결과 같은 과냉도에서 상평형은 THF가 우수하였으며, 하이드레이트 생성에 소모되는 가스소모량은 산화탄소나노튜브가 월등히 우수한 효과를 보였다. 따라서 이 두 종류 촉진제의 단점을 보완하고, 우수한 효과를 이끌어 내기 위해 THF와 산화탄소나노튜브를 혼합하였다. 0.003 wt%의 산화탄소나노유체에 5.56 mol%의 THF를 혼합하였으며, 하이드레이트 상평형, 가스소모량, 생성시간을 측정하여 증류수와 THF, 산화탄소나노유체와 비교하였다. 그 결과, THF+산화탄소나노튜브 혼합유체의 상평형은 THF의 상평형과 비슷하였으고, 과냉도 3.4K에서의 가스소모량은 산화나노유체가 증류수의 3.6배, THF가 증류수의 1.7배, THF+산화탄소나노튜브 혼합유체가 증류수의 5.2배로 THF+산화탄소나노튜브 혼합유체에서 가스소모량이 가장 높음을 알 수 있었다. 또한 하이드레이트 생성시간은 같은 과냉도에서 THF+산화탄소나노튜브 혼합유체가 THF보다 빠르며, 산화탄소나노유체의 하이드레이트 생성시간과 비슷함을 보였다. 따라서 THF+산화탄소나노튜브 혼합유체는 THF의 우수한 상평형 효과와 탄소나노튜브의 높은 가스소모량 효과를 같이 가지고 있음을 확인하였다.

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Development of Optimized Driving Model for decreasing Fuel Consumption in the Longitudinal Highway Section (고속도로 종단지형을 고려한 연료 효율적 최적주행전략 모형 개발)

  • Choi, Ji-eun;Bae, Sang-hoon
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.14 no.6
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    • pp.14-20
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    • 2015
  • The Korea ministry of land, infrastructure and transport set the goal of cutting greenhouse gas emissions from the transport sector by 34.3% relative to the business as usual scenario by 2020. In order to achieve this goal, support is being given to education and information regarding eco-driving. As a practical measure, however, a vehicle control strategy for decreasing fuel consumptions and emissions is necessary. Therefore, this paper presents an optimized driving model in order to decrease fuel consumption. Scenarios were established by driving mode. The speed profile for each scenario applied to Comprehensive Modal Emission Model and then each fuel consumption was estimated. Scenarios and speed variation with the least fuel consumption were derived by comparing the fuel consumptions of scenarios. The optimized driving model was developed by the derived the results. The speed profiles of general driver were collected by field test. The speed profile of the developed model and the speed profile of general driver were compared and then fuel consumptions for each speed profile were analyzed. The fuel consumptions for optimized driving were decreased by an average of 11.8%.

A Low Power ROM using Charge Recycling and Charge Sharing (전하 재활용과 전하 공유를 이용한 저전력 롬)

  • 양병도;김이섭
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.7
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    • pp.532-541
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    • 2003
  • In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.