• Title/Summary/Keyword: 셀 버퍼

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화합물 반도체 Cu(InGa)Se2박막 태양전지의 제작과 태양광발전 활용

  • Kim, Je-Ha;Jeong, Yong-Deok;Bae, Seong-Beom;Park, Rae-Man;Han, Won-Seok;Jo, Dae-Hyeong;Lee, Jin-Ho;Lee, Gyu-Seok;Kim, Yeong-Seon;O, Su-Yeong
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2009.05a
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    • pp.8.2-8.2
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    • 2009
  • 구리(Cu)-인듐(In)-갈륨(Ga)-셀레늄(Se)의 4 원소 화합물 반도체인 Cu(InGa)$Se_2$ (CIGS) 태양전지 세계 최고 셀효율은 2008년 현재 19.9% 로서 박막형 태양전지 중 가장 높은 효율을 보이고 있다. 이는 다결정(폴리) 실리콘 태양전지의 20.3%와 대등한 수준이다. 이 CIGS 태양전지는 제조단가를 표준 결정형 실리콘 태양전지 대비 50% 대로 획기적으로 낮출 수 있어 가장 경쟁력이 있는 차세대 재료로 꼽히고 있다. 본 연구에서는 CIGS태양전지를 고진공 물리 증작법으로 제작하였으며 표면과 박막의 순도를 외부오염을 방지하기 위하여 후면전극, 광흡수체 및 전면전극을 동일 진공에서 제작할 수 있는 멀티 챔버 클러스터 증착 시스템을 이용하였다. 기판으로 소다라 임유리, 후면전극으로 Mo, 전면전극으로 I-ZnO/Al:ZnO 및 ITO를 이용하였다. 버퍼층으로 CdS를 chemical bath deposition (CBD)를 이용하였다. 소자는 무반사막을 사용하지 않고 Al/Ni전극 그리드를 이용하였다. 이 소자로부터 0.22 $cm^2$에서 16%의 효율을 얻었다. 각 박막층 간 계면의 분석을 전기적인 특성, ellisometry에 의한 광특성, 표면과 결정성에 대한 SEM 및 XRD의 특성을 보고한다. 또한, 대표적 화합물 반도체 박막 태양전지인 CIGS 태양전지의 기술의 현황, 학문적인 과제 및 실용화의 문제점을 발표하기로 한다.

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MASK ROM IP Design Using Printed CMOS Process Technology (Printed CMOS 공정기술을 이용한 MASK ROM 설계)

  • Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.788-791
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    • 2010
  • We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

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A Study on Improving the Fairness by Dropping Scheme of TCP over ATM (ATM상의 TCP 패킷 폐기정책에 따른 공정성 개선에 관한 연구)

  • Yuk, Dong-Cheol;Park, Seung-Seob
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.11S
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    • pp.3723-3731
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    • 2000
  • Recently, the growth of applications and services over high-speed Internet increase, ATM networks as wide area back-bone has been a major solution. The conventional TCP suite is still the standard protocol used to support upper application on current Internet and uses a window based protocol for flow control in the transport layer. When TCP data uses the UBR service in ATM layer, the control method is also buffer management. If a cell is discarded in ATM layer. one whole packet of TCP will be lost. Which is responsible for most TCP performance degradation and do not offer sufficiently QoS. To solve this problem, Several dropping strategies, such as Tail Drop, EPD, PPO, SPD, FBA, have been proposed to improve the TCP performance over ATM. In this paper, to improve the TCP fairness of end to end, we propose a packet dropping scheme algorithm using two fixed threshold. Under similar condition, we compared our proposed scheme with other dropping strategies. Although the number of VC is increased, simulation results showed that the proposed scheme can allocate more fairly each VC than other schemes.

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A Study on Reactive Congestion Control with Loss Priorities in ATM Network (ATM 네트워크에서 우선권을 갖는 반응 혼잡 제어에 관한 연구)

  • Park, Dong-Jun;Kim, Hyeong-Ji
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.4
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    • pp.697-708
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    • 1996
  • In this paper, we study reactive congestion control with priority in ATM network. The priority schemes for buffer access, partial buffer sharing have been investigated in order to improve the utilization of ATM network resources the network and to satisfy the most demanding traffic class. We consider in this paper a discrete-time queueing model for partial buffer sharing with two Markov modulated Poisson inputs. This model can be used to analyze the the effects of the partial buffer sharing priority scheme on system performance for realistic cases of bursty services. Explicit formulae are derived for the number of cells in the system and the loss probabilities for the traffic. Congestion may still occur because of unpredictable statistical fluctuation of traffic sources even when preventive control is performed in the network. In this Paper, we study reactive congestion control, in which each source changes its cell emitting rate a daptively to the traffic load at the switching node. Our intention is that,by incorporating such a congcstion control method in ATM network,more efficient congsestion control is established. We develope an analytical model,and carry out an approximateanalysis of reactive congestion con-trol with priority.Numerical results show that several orders of magnitude improvement in the loss probability can be achieved for the high priority class with little impact on the low priority class performance.And the results show that the reactive congestion control with priority are very effective in avoiding congestion and in achieving the statistical gain.

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Parallel Testing Circuits with Versatile Data Patterns for SOP Image SRAM Buffer (SOP Image SRAM Buffer용 다양한 데이터 패턴 병렬 테스트 회로)

  • Jeong, Kyu-Ho;You, Jae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.9
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    • pp.14-24
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    • 2009
  • Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

Fuzzy-based ABR Traffic Control Algorithm in VS/VD Switch (VS/VD 구조의 퍼지 기반 ABR 트래픽 제어에 관한 연구)

  • Park, Hyun;Jeong, Kwang-Il;Cheong, Myung-Soo;Chung, Kyung-Taek;Chon, Byoung-Sil
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.39 no.8
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    • pp.7-13
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    • 2002
  • In this paper, we propose an traffic control algorithm for efficient link utilization of ATM-ABR service based on fuzzy logic. The proposed algorithm, controls transmission rates of source according to switch buffer size and input cell tate by using the fuzzy rate . For this method we developed a model and algorithm of fuzzy traffic control method and fuzzy traffic controller which based on ER of VS/VD. For the fuzzy traffic controller, we also designed a membership function, fuzzy control rules, and a max-min inferencing method.

A Hybrid UPC Algorithm Combining Leaky Bucket and EWMA Algorithms on ATM Networks (ATM 망에서 리키버켓과 EWMA 방식을 결합한 복합형 UPC 알고리즘)

  • Yun, Seok-Hyeon;Seong, Yeong-Rak;O, Ha-Ryeong
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.11
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    • pp.1382-1390
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    • 1999
  • 본 논문에서는 ATM 망에서 대표적 사용 파라미터 제어(UPC) 알고리즘인 리키버켓 알고리즘과 윈도우 알고리즘의 하나인 EWMA 알고리즘을 결합한 복합형 UPC 알고리즘을 제안하고 그 성능을 평가 분석하였다.제안된 알고리즘은 최대전송율을 제어하는 리키버켓과 평균전송율을 제어하는 EWMA를 병렬로 결합하여, 최대전송율과 평균전송율을 동시에 고려하였다. ON/OFF 트래픽 소스 모델을 적용, BONeS를 이용하여 모의실험한 결과 제안 알고리즘이 기존의 리키버켓 알고리즘에 비해 셀 손실율과 버퍼 크기면에서 우수한 성능을 나타냈다.Abstract In this paper, a hybrid UPC algorithm is proposed, which combines the representative Leaky Bucket UPC algorithm with the EWMA window algorithm in the ATM network and then its performance is evaluated. The hybrid UPC algorithm is made up of Leaky Bucket and EWMA, which control the peak bit rate and the mean bit rate, respectively. According to the result of the simulation using BONeS with the On/Off traffic source model, it is revealed that the proposed UPC algorithm has superior performance to the existing Leaky Bucket UPC algorithm with regard to both the cell loss rate and the buffer size.

Performance Analysis of a WCSFQ (Weighted Core-Stateless Fair Queueing)-like Space Priority Policy for ATM nodes (ATM 노드를 위한 WCSFQ-유사 공간 우선순위 정책의 성능분석)

  • Kang, Koo-Hong
    • The KIPS Transactions:PartC
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    • v.12C no.5 s.101
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    • pp.687-694
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    • 2005
  • In ATM and W networks, high Priority Packets should be selectively favored over low Priority Packets in case of congestion. For this purpose, we introduce a space priority policy for ATM nodes in this paper which is very similar to the weighted core-stateless fair queueing(WCSFQ) in IP nodes. We also analyze the loss probabilities for different classes of cells for MMPP/D/1/K with a threshold level, and discuss the numerical results. The numerical results illustrate that the WCSFQ scheme can be used to support the differentiated services in ATM or IP nodes.

A Study on Basic Technologic for File Transmission Between Base-Station and Mobile Hosts (베이스 스테이션과 모빌 호스트간의 파일전송 기초기술연구)

  • 김창식;김정원;정기동
    • Journal of Korea Multimedia Society
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    • v.2 no.1
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    • pp.59-68
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    • 1999
  • Multimedia applications have an ability to transmit a lot of data in real time. In mobile circumstances the replay of continuous multimedia data in real time causes frequent replay breaks and poor service quality because of low transmission speed and new transmission path settings in hand-off. To avoid these unfavorable side effects, we need a new mechanism which can transmit data efficiently between base station and mobile hosts, to control the buffers of mobile hosts, and to switch to a new transmission path rapidly in hand-off. The study is to propose how to give good service to mobile hosts during hand-off and the mechanism which can increase the number of mobile hosts in the cell unit.

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A New Criterion of Cell Discard in an ATM Switch with Input and Output Buffers (입출력버퍼형 ATM 교환기의 셀 폐기 방법에 대한 새로운 기준 제안 및 성능 분석)

  • Gwon, Se-Dong;Park, Hyeon-Min;Choe, Byeong-Seok;Park, Jae-Hyeon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.4
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    • pp.1246-1264
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    • 2000
  • An input-output buffering switch operates in either of tow different cell loss modes; Backpressure mode and Queueloss mode. In the previous studies, the Backpressrue mode is more effective at low traffic loads, and the Queueloss mode performs better at high traffic. We propose a new operation mode, called Hybrid mode, which adopts the advantages of he Backpressure and the Queueloss mode. Backpressure and Queueloss modes are distinguished from whether a cell loss occurs at the output buffer or not when output buffer overflows, irrespective of input buffer status. In order to simply combine Backpressure and Queueloss mode, the change of input traffic load must be measured. However, in the Hybrid mode, simply both of the input and output buffer overflow and checked out to determine the cell discard. The performance of the Hybrid mode is compared with those of the Backpressure and the Queueloss mode under random and bursty traffic. This paper show that the Hybrid mode always gives the best performance results for most ranges of load values.

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