• Journal of the Korean Chemical Society
• /
• v.50 no.1
• /
• pp.14-22
• /
• 2006

the basic model of chemical reactor using glow discharge, we used cathode discharge cell with vacant cavity in the middle. Currently glow discharge is widely studied as a radiation source or atomization device in atomic spectroscopy and remarkable technological achievements are made through the graft with other analysis devices such as microanalysis and steel analysis.1 Additionally, as the characteristics of basic glow discharge and radiation have been reviewed many times, those results could be used in this experiment.2-3 In 1993, an article regarding the treatment of poisonous gas in the air using low temperature plasma was published. According to this article, if DC Glow Discharge is used under continuous atmospheric flow, poisonous gases such as SO2 and NO can be removed.4 Based on those findings, we designed highly efficient reactor where stable air plasma is composed and all air flow pass the negative glow area passing through the tube. It was observed that the cathode tube type glow discharge developed in this study would be economical, easy to use and could be used as radiation source as well.

• Food Science and Preservation
• /
• v.14 no.5
• /
• pp.451-456
• /
• 2007

The vitamin C content in extruded comstarch matrix was shown to depend on extrusion process variables (barrel temperature and water content), the packaging method, and the storage period. In addition, loss rates of vitamin C under different processing conditions were calculated. Extrusion process variable were barrel temperature ($80^{\circ}C,\;90^{\circ}C,\;100^{\circ}C$ and $110^{\circ}C$), and water content (25% 30% both w/w). The vitamin C content decreased as barrel temperature increased from $80^{\circ}C$ to $110^{\circ}C$ and water content increased from 25% to 30% when either LDPE plastic film packaging or ON film vacuum packaging were employed. As barrel temperature and water content increased, vitamin C decreased in comstarch packed in either LDPE film or ON film. As temperature increased, vitamin C loss rate increased under both packaging conditions, but the loss tate was only 50% of the LDPE film packaging rate when ON film vacuum packaging was used. In conclusion, the higher the temperature, and the greater the water content, the less vitamin C was inactivated during extrusion cooking, although the loss rah of vitamin C became faster as temperature and water content rose. In conclusion, extrusion process could be applied for making vitamin C matrix to extend vitamin C preservation.

• Composites Research
• /
• v.28 no.4
• /
• pp.219-225
• /
• 2015

Air spoiler, which can reduce the drag during operation, can be considered as a possible means to reduce carbon dioxide emission and to increase fuel efficiency. In this study, a composite air spoiler was designed and tested by static and repeated loads. The Green Water Pressure of 0.1 MPa a ship experiences during operation was perpendicularly applied to the air spoiler. Air spoiler was manufactured with sandwich panel which has glass fabric face and balsa core. Multiple sandwich panels were assembled to steel frame by bolt joint. The joint was designed to have bearing failure and examined by static and fatigue tests. Tests showed that the designed joint has enough margin of safety to endure joint failure. The developed sandwich panel to air spoiler is planned to be applied to a large scale commercial ship.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.9 no.4
• /
• pp.427-438
• /
• 1998

The bit error rate(BER) performance of Trellis Coded QPSK signal in the presence of cochannel interference (CCI) and Rician fading is investigated. The trellis coded QPSK system adopts Maximum Ratio Combining (MRC) diversity reception and Reed-Solomon code to enhance system performance. Using the derived error probability equation, the error performance of trellis coded QPSK system has been evaluated and shown in figures to discuss as a function of signal power to noise power ratio (SNR), signal power to interference power ratio(SIR), direct to indirect signal power ratio ($K_R$), the number of diversity branch (M), the frame length of Reed-Solomon code (n), the number of error correction symbol (t), and the number of state of trellis encoder. From the results, we know that proposed system is affected by cochannel interference and fading in microcell environment. Also, BER performance of Trellis Coded QPSK system can be improved as increasing either the power of desired signal or the value of SIR. And the BER floor in microcellular system is caused by the cochannel interference and it occurs at high BER when SIR is low. And Reed-Solomon code (n=15, t=2) is more effective to restrain the affection of CCI and fading than MRC diversity reception (M=2).

• Journal of the Korean Society of Food Science and Nutrition
• /
• v.46 no.10
• /
• pp.1195-1204
• /
• 2017

This study was designed to determine the effects of three cooking methods, boiling, microwave, and steaming, on elemental compositions of green pumpkin, zucchini, and sweet and ripened pumpkin. The cooking methods were carried out at 3, 5, and 10 min. The samples were then dried, crushed, and decomposed by microwave-assisted digestion method. Macro elements were analyzed by Inductively Coupled Plasma-Optical Emission Spectrometer (ICP-OES), whereas ICP-Mass Spectrometer (ICP-MS) was used for micro elements determination. From the results, macro elements were present in the order of K, P, Ca, Mg, S, Fe, Zn, and Na in all analyzed pumpkins. Among micro elements, Mn, Cu, Rb, and Ba, were present at high levels. For the effects of cooking methods, boiling significantly reduced the concentrations of elements. Cooking time affected concentrations of elements in the same manner with large differences between elemental contents in samples cooked for 5 and 10 min. Regarding micro elements contents, both effects were not significant. Similar elemental compositions with different concentration levels in all pumpkin types were observed. Green pumpkin and ripened pumpkin showed high retention rates of inorganic components upon steaming, and zucchini and sweet pumpkin showed high retention rates upon microwave cooking. Conclusively, cooking method and time affect amounts of residual inorganic ingredients in pumpkin.

• Journal of the Korean Geographical Society
• /
• v.51 no.5
• /
• pp.651-665
• /
• 2016

This paper tried to delimitate the location and scope of Nokdundo located in the Dumangang estuary. In 18th century, Nokdundo was an alluvial island formed by several tributaries divided from the mainstream of Dumangang. In the mid-19th century, Nokdundo was connected to the Russian territory because some tributaries were blocked by sediment flows. In many maps published in the Joseon Dynasty, the location and size of Nokdundo had not been depicted consistently with each other nor been described correctly. Because of the recurrent extinction-generating phenomena of waterways of the Dumangang due to sedimentation process, the location and scope of Nokdundo can be delimitated differently according to the era. According to the distance information of the records published in the 19th and 20th century, the scope of Nokdundo can be extended widely to the Maritime Province of Siberia. So, the author have set the Sodumangang(Karasik River) as the northern boundary of Nokdundo. The Karasik River is called Sodumangang by the Koreans living in the Maritime Province. As a tributary of the Dumangang, Sodumangang flows into the Posyet Bay. Nokdundo was an island separated from the Korean peninsula and the Maritime Province by the Dumangang and the Sodumangang respectively. Tributaries of the Dumangang have formed many alluvial islands at the mouth of Dumangang where the Dumangang meets with the East Sea. So, the possibility that Nokdundo was consisted of several islands can not be excluded.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1107-1114
• /
• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.2
• /
• pp.335-342
• /
• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.401-404
• /
• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.875-878
• /
• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.