• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1760-1762
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• 2010

본 논문에서 3치가산기와 승산기(multiplier)는 전류모드 CMOS에 의해서 구현된다. 첫째, 3치 T-gate를 집적회로 설계의 유효 가용성을 갖고 있는 전류모드 CMOS를 이용하여 구현한다. 둘째, 3치 T-gates를 이용해 회로가 유한체 GF (3)에 대하여 2변수 3치 가산표 (2-variable ternary addition table) 및 구구표 (multiplication table)가 실현되도록 구현한다. 마지막으로, 이러한 동작 회로들은 1.5 CMOS 표준 기술과 $15{\mu}A$ 단위전류(unit current) 및 3.3V 소스 전압 (VDD voltage)에 의해 활성화 된다. 활성화 결과는 만족할 만한 전류 특성을 나타냈다. 전류 모드 CMOS에 의하여 실행되는 3치가산기 및 승산기는 단순하며 와이어 라우팅(wire routing)에 대하여 정규적이고, 또한 셀 배열 (cell array)과 함께 모듈성 (modularity)의 특성을 갖고 있다.

• Geophysics and Geophysical Exploration
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• v.13 no.1
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• pp.118-127
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• 2010

Resistivity logging instruments are designed to measure the electrical resistivity of a formation, and this can be directly interpreted to provide a water-saturation profile. However, resistivity logs are sensitive to borehole and shoulder-bed effects, which often result in misinterpretation of the results. These effects are emphasised more in the presence of tool eccentricity. For precise interpretation of short- and long-normal logging measurements in the presence of tool eccentricity, we simulate and analyse eccentricity effects by combining the use of a Fourier series expansion in a new system of coordinates with a 2D goal-oriented high-order self-adaptive hp finite-element refinement strategy, where h denotes the element size and p the polynomial order of approximation within each element. The algorithm automatically performs local mesh refinement to construct an optimal grid for the problem under consideration. In addition, the proper combination of h and p refinements produces highly accurate simulations even in the presence of high electrical resistivity contrasts. Numerical results demonstrate that our algorithm provides highly accurate and reliable simulation results. Eccentricity effects are more noticeable when the borehole is large or resistive, or when the formation is highly conductive.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.26-33
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• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Archives of design research
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• v.19 no.5 s.67
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• pp.85-94
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• 2006

In the 2000s, character animation technique is used at domestic TV character animation ads of diverse items displaying new character patterns and expression techniques of a high level. This study intends to identify the characteristics of TV character animation ads based ell character aesthetic theory and advertising rhetoric theory, and based on these findings, analyze trend and stream of expression in TV character animation ads by examining and classifying advertisements released in the past four years by items, character patterns and expression techniques. The results showed that TV character animation ads have been concentrated on confectionery, beverages and foods in the past, but the items have been diversified through the years. With reference to character patterns, personal and animal characters had made the main pattern, but recently product, virtual and composite characters are on the increase. In expression techniques, cell animation technique was found to be the most frequently used technique, which was followed by full-3D, cell and live action, cell and 3D and the clay animation technique. A trend like this suggests that TV character animation advertising items will continue to increase in line with the participation level of targets. In the meantime, personal and animal characters will continue to make the leading character pattern, while virtual and composite character patterns emerge in new forms. In expression techniques, live action combined with 30 technique and techniques using new expression materials will appear with cell animation technique as a central figure. As a whole, Korean character animation advertisement is expected to keep on growing to a new dimension in the aspect of items, character patterns and expression technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.306-313
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• 2012

In order to enhance the isolation level between two dual-band E-slot microstrip patch antennas, EBG structure which operates in UMTS Tx(1.92~1.98 GHz) and Rx(2.11~2.17 GHz) band is proposed. The proposed EBG structure made with a periodic array of two different size EBG unit cells which has a modified mushroom-type for isolation improvement between two antennas. They do not share a common ground plane of the microstrip patch antenna. Overall size of the fabricated antenna is $210.5mm{\times}117mm$. The two different EBG unit cell sizes are $15.6mm{\times}4mm$ and $17.4mm{\times}4mm$, respectively. It was etched on the FR-4 substrate(thickness=3.93 mm, ${\varepsilon}_r$=4.6). The experiment results show that the isolation level between antennas in Tx/Rx band were improved by about 9 dB and 12 dB, respectively, through the use of the proposed EBG structure.

• Journal of the Korean Society of Marine Environment & Safety
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• v.19 no.4
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• pp.410-415
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• 2013

Acoustic target strength (TS) is one of the most considerable design elements for survival capacities of the submarine. It needs to reduce acoustic TS that submarines are getting larger and larger, Alberich anechoic coatings are widely used as the representative method. In this paper, the finite element method (FEM) is used to analyze the reflection and transmission coefficients of Alberich anechoic coatings, which have periodic unit cells. The FEM results are compared with experimental results in the literature. Moreover, acoustic TS for the submarine is analyzed by using that result. Finally, it is shown that acoustic TS (Case 1: 10dB, Case 2: 6dB) are reduced due to the use of Alberich anechoic coatings.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.2
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• pp.95-104
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• 2011

In this paper, the metamaterial transmission line (TL) based on the complementary spiral resonators (CSRs) and interdigital structure is presented for reducing the phase noise of the voltage-controlled oscillator (VCO). The metamaterial TL is realized by adopting the array of the CSRs etched on the ground plane and the interdigital transmission line on the signal plane. The interdigital TL on the signal plane has been used to obtain higher Q value than the conventional TL without the interdigital structure. The resonance properties and inherent saturation of Q value of the proposed metamaterial TL have been analyzed by varying the width of the TL on the signal plane, dimensions of the CSRs, current directions between the CSRs, number of the unit cell-pair of the CSRs, and whether or not there is the interdigital structure in this paper. The phase noise and tuning range of the proposed VCO are -127.50~-125.33 dBc/Hz at 100 kHz and 5.744~5.852 GHz.