• Journal of KIISE:Software and Applications
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• v.26 no.12
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• pp.1428-1444
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• 1999

MSC는 ITU에 의해 표준화된, 병행 시스템의 명세를 기술하기 위한 그래픽 형태와 텍스트 형태를 제공하는 언어로서 실시간 시스템 특히 통신 교환 시스템의 특성을 기술하기 위해 자주 사용된다. 통신 시스템이 제대로 동작함을 보이기 위해서는 정형적인 방법을 사용하여 시스템 행위를 검증할 필요가 있다. 통신 소프트웨어를 검증하는 방법 중 하나의 방법으로 유한 상태를 기반으로 하는 방법이 있다. 유한 상태를 기반으로 하는 방법에서는 먼저 시스템 명세에 해당하는 전체 상태 전이 그래프를 생성한 후 이를 바탕으로 model-checking 등의 방법을 사용하여 시스템의 특성을 검증한다. 본 논문에서는 MSC로 기술된 통신 소프트웨어 명세로부터 전체 상태 전이 그래프를 생성하는 방법에 초점을 맞추었다. 시스템 명세에 해당하는 상태 전이 그래프를 생성하기 위해 보다 직관적으로 MSC의 의미론을 표현할 수 있고, 또한 쉽게 전체 상태 전이 그래프를 생성할 수 있는 행위 종속 그래프를 제안하였다. MSC 명세는 일단 행위 종속 그래프로 변환이 되고 이 행위 종속 그래프를 이용하여 전체 상태 전이 그래프가 생성된다.Abstract Message Sequence Chart (MSC) standardized by International Telecommunication Union is a graphical and textual language for describing the specification of concurrent systems. It is frequently used both formally and informally for specifying the behavior of real-time systems, in particular telecommunication switching systems. To ensure that a communication system operates properly, the verification process showing the correctness of system's behavior formally is necessary. One of the verification methods is a finite-state method. In the finite-state method, the global state transition graph (GSTG) is constructed and then safety and liveness properties of systems are verified through a well-known method such as model checking. In this paper, we forcus on the construction of GSTG from the specifications of telecommunication software written in MSC. We suggest Action Dependency Graph (ADG) which can present the semantics of MSC intuitively and also provide a GSTG construction method from ADG. MSC specifications are translated to ADGs and, in turns, the GSTGs are constructed by using these ADGs.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2430-2441
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• 2000

A visual concurrent programming environment, called ESTGVP is designed and implemented, which is easy to understand, highly portable, and can represent parallel behaviors. For our purpose, a conventional state transition graph is extended so as to enable both of synchronous and asynchronous parallel operations. We call it extended state transition graph (ESTG). ESTGVP uses the ESTG and texts for programming, and makes it easy programming sequential and parallel behaviors. Also, it is easy to understand the control structure of a program because ESTGVP is a visual programming environment based on the graph. ESTGVP is written in Tel language and thus it is highly portable on various operating systems. It consists of three major components; edition, transformation and execution. If necessary, ESTG can be transformed into C or Tel language, and its execution is based on Tel.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.110-123
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• 2001

본 논문에서는 자유 선택 신호 전이 그래프와 비동기 유한 상태기로 기술된 회로 명세로부터 직접 속도 독립 회로를 합성하는 시스템에 대해 기술한다. 기존의 상태 그래프 기반의 합성 시스템은 상태의 수가 지수승으로 증가할 수 있기 때문에 큰 규모의 회로에 대해서는 합성에 실패할 수 있다는 문제점을 가지고 있다. 이를 해결하기 위해 여러 직접 합성 방법들이 제안되었는데, 본 논문의 합성 시스템은 마크드 그래프 분할 방법과 임시 전이의 사용을 허용함으로써 합성할 수 있는 회로의 범위를 넓혔다. 기존의 벤치마크 회로에 대한 실험결과 본 합성 시스템은 기존의 상태 그래프 기반의 합성 시스템에 비하여 현저하게 수행 속도를 단축시킬 수 있었고 기존의 직접 합성 시스템에 비하여 보다 확장된 그리고 보다 실용적인 회로 명세를 처리할 수 있었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.2
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• pp.105-111
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• 2005

Though GF(2) CA can only handle data with bit units GF(2p) CA can handle data with units more than bit units. In this paper we analyze the state-transition of nongroup cellular automata(CA) with a single attractor over GF(2p). And we propose the constructing method the state-transition diagram of a linear SACA over GF(2p) by using the concept of basic path. Also we propose the state-transition diagram of the nonlinear complemented SACA by using the state-transition diagram of a linear SACA.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.513-516
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• 2005

셀룰라 오토마타가 비트단위로 데이터가 처리되는데 비하여 계층적 셀룰라 오토마타는 바이트 단위 또는 그 이상의 단위로 데이터를 처리할 수 있다. 본 논문에서는 GF($2^p$) 위에서의 유한체 성질을 이용하여 한 개의 트리로 구성되는 계층적 비그룹 셀룰라 오토마타인 SAHCA의 성질에 대하여 분석한다. 또한 기본경로를 이용한 선형 SAHCA의 상태전이 그래프를 구성하는 방법과 선형 SAHCA의 상태전이 그래프를 이용하여 비선형인 여원 SAHCA의 상태전이 그래프를 구성하는 알고리즘을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11B
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• pp.1020-1029
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• 2008

This paper proposes an high speed pattern matching algorithm and its implementation. The pattern matcher is used to check patterns from realtime input packet. The proposed algorithm can find exact string, range of string values, and combination of string values from input packet at high speed. Given string and rule set are modelled as a state transition graph which can find overlapped strings simultaneously, and the state transition graph is partitioned according to input implicants to reduce implementation complexity. The pattern matcher scheme uses the transformed state transition graph and input packet as an input. The pattern matcher was modelled and implemented in VHDL language. Experimental results show the proprieties of the proposed approach.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.71-81
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• 2010

In a typical web environment, it is difficult to determine the update and re-computation status of WebView content or the transition of WebView processing included in web page. If an update to one of data is performed before a read operation to that, we could get a wrong result due to the incorrect operation and increase a complexity of the problem to process. To solve this problem, lots of researchers have studied and most of these problems at the single user environment is not problems. However, the problems at a distributed environment might be occurred. For this reason, in this paper, we proposed the extended state transition graph and algorithms for each status of WebView for explaining WebView state in the distributed environment and analyze the performance of using the materialized WebView and not. Additionally, also analyze the timing issues in network and effectiveness which follows in size of WebView contents.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.216-226
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• 2000

This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic signal transition graph specification with timing constraints. First, a timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding paths in the graph. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates circuits that have nearly the same area as compared to previous methods.