• Title/Summary/Keyword: 비트-병렬 곱셈기

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Low Complexity Digit-Parallel/Bit-Serial Polynomial Basis Multiplier (저복잡도 디지트병렬/비트직렬 다항식기저 곱셈기)

  • Cho, Yong-Suk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.4C
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    • pp.337-342
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    • 2010
  • In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

Digit-Parallel/Bit-Serial Multiplier for GF$(2^m)$ Using Polynomial Basis (다항식기저를 이용한 GF$(2^m)$ 상의 디지트병렬/비트직렬 곱셈기)

  • Cho, Yong-Suk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.11C
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    • pp.892-897
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    • 2008
  • In this paper, a new architecture for digit-parallel/bit-serial GF$(2^m)$ multiplier with low latency is proposed. The proposed multiplier operates in polynomial basis of GF$(2^m)$ and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

Design of Bit-Parallel Multiplier over Finite Field $GF(2^m)$ (유한체 $GF(2^m)$상의 비트-병렬 곱셈기의 설계)

  • Seong, Hyeon-Kyeong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1209-1217
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    • 2008
  • In this paper, we present a new bit-parallel multiplier for performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the vector code generator(VCG) to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of VCG have two AND gates and two XOR gates. Using these VCG, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the VCGs with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI.

A Hybrid type of multiplier over GF(2$^m$) (GF(2$^m$)상의 하이브리드 형식의 곱셈기)

  • 전준철;유기영
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.04a
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    • pp.275-277
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    • 2003
  • 본 논문에서는 GF(2$^{m}$ )상에서 비트 직렬 Linear Feedback Shift Register (LFSR) 구조와 비트 병렬 셀룰라 오토마타(Cellular Automata, CA)구조를 혼합한 새로운 하이브리드(Hybrid) 형식의 A$B^2$곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 제곱연산을 위해 구조적으로 가장 간단한 비트 직렬 구조를 이용하고, 곱셈연산을 위해 시간 지연이 적은 비트 병렬 구조를 이용한다. 제안된 구조는 LFSR의 구조적인 특징과 Periodic Boundary CA (PBCA)의 특성, 그리고 All One Polynomial (AOP)의 특성을 조화시킴으로써 기존의 구조에 비하여 정규성을 높이고 지연 시간을 줄일 수 있는 구조이다. 제안된 곱셈기는 공개키 암호화의 핵심이 되는 지수기의 구현을 위한 효율적인 기본구조로 사용될 것으로 기대된다.

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Low Space Complexity Bit-Parallel Shifted Polynomial Basis Multipliers using Irreducible Trinomials (삼항 기약다항식 기반의 저면적 Shifted Polynomial Basis 비트-병렬 곱셈기)

  • Chang, Nam-Su;Kim, Chang-Han
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.20 no.5
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    • pp.11-22
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    • 2010
  • Recently, Fan and Dai introduced a Shifted Polynomial Basis and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. As the name implies, the SPB is obtained by multiplying the polynomial basis 1, ${\alpha}$, ${\cdots}$, ${\alpha}^{n-1}$ by ${\alpha}^{-\upsilon}$. Therefore, it is easy to transform the elements PB and SPB representations. After, based on the Modified Shifted Polynomial Basis(MSPB), SPB bit-parallel Mastrovito type I and type II multipliers for all irreducible trinomials are presented. In this paper, we present a bit-parallel architecture to multiply in SPB. This multiplier have a space complexity efficient than all previously presented architecture when n ${\neq}$ 2k. The proposed multiplier has more efficient space complexity than the best-result when 1 ${\leq}$ k ${\leq}$ (n+1)/3. Also, when (n+2)/3 ${\leq}$ k < n/2 the proposed multiplier has more efficient space complexity than the best-result except for some cases.

Parallelism of the bit-serial multiplier over Galois Field (유한체 상에서 비트-직렬 곱셈기의 병렬화 기법)

  • 최영민;양군백
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.3B
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    • pp.355-361
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    • 2001
  • 유한체(Galois Field) 상에서의 곱셈(multiplication)을 구현하는 방법은 크게 병렬 곱셈기(parallel multiplier)와 직렬 곱셈기(serial multiplier)로 나누어질 수 있는데, 구현시 하드웨어 면적을 작게 차지한다는 장점 때문에 직렬 곱셈기가 널리 사용된다. 하지만 이 직렬 곱셈기를 이용하여 계산을 하기 위해서는 병렬 곱셈기에 비해 많은 시간이 필요하게 된다. 직렬기법과 병렬기법의 결합이 이를 보완할 수 있게 된다. 본 논문에서는 복잡도는 직렬 곱셈기와 큰 차이가 없으면서 연산시간을 줄인 곱셈기*(multiplier)를 제안하였다. 이 곱셈기를 사용하면 복잡도는 크게 늘어나지 않았으면서 유한체 상에서의 곱셈을 하는데 필요한 시간을 줄이는 효과를 얻을 수 있다.

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Efficient bit-parallel multiplier for GF(2$^m$) defined by irreducible all-one polynomials (기약인 all-one 다항식에 의해 정의된 GF(2$^m$)에서의 효율적인 비트-병렬 곱셈기)

  • Chang Ku-Young;Park Sun-Mi;Hong Do-Won
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.7 s.349
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    • pp.115-121
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    • 2006
  • The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

A Fast 64$\times$64-bit Multiplier for Crypto-Processor (암호 프로세서용 고속 64$\times$64 곱셈기)

  • 서정욱;이상흥
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1998.12a
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    • pp.471-481
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    • 1998
  • 피승수를 승수로 곱하는 곱셈연산은 승수에 대한 많은 부분곱을 더하기 때문에 본질적으로 느린 연산이다. 특히, 큰 수를 사용하는 암호 프로세서에서는 매우 빠른 곱셈기가 요구된다. 현재까지 느린 연산의 개선책으로 radix 4, radix 8, 또는 radix 16의 변형 부스 알고리즘을 사용하여 부분곱의 수를 줄이려는 연구와 더불어 Wallace tree나 병렬 카운터를 사용하여 부분곱의 합을 빠르게 연산하는 방법이 연구되어 왔다. 본 논문에서는 암호 프로세서용 64$\times$64 비트 곱셈기를 구현하는데 있어서, 고속의 곱셈을 위하여 고속의 병렬 카운터를 제안하였으며, radix 4의 변형 부스 알고리즘을 이용하여 부분합을 만들고 부분합의 덧셈은 제안한 카운터를 사용하였다. 64$\times$64 비트 곱셈기를 구현함에 있어서 본 논문에서 제안된 카운터를 이용하는 것이 속도 면에서 Wallace scheme또는 Dadda scheme을 적용하여 구현하는 것 보다 31% 정도, Mehta의 카운터를 적용하여 구현하는 것 보다 21% 정도 개선되었다.

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(Design of GF(216) Serial Multiplier Using GF(24) and its C Language Simulation (유한체 GF(24)를 이용한 GF(216)의 직렬 곱셈기 설계와 이의 C언어 시뮬레이션)

  • 신원철;이명호
    • Journal of the Korea Society of Computer and Information
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    • v.6 no.3
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    • pp.56-63
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    • 2001
  • In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

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Efficient Bit-Parallel Polynomial Basis Multiplier for Repeated Polynomials (반복 기약다항식 기반의 효율적인 비트-병렬 다항식 기저 곱셈기)

  • Chang, Nam-Su;Kim, Chang-Han;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.19 no.6
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    • pp.3-15
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    • 2009
  • Recently, Wu proposed a three small classes of finite fields $F_{2^n}$ for low-complexity bit-parallel multipliers. The proposed multipliers have low-complexities compared with those based on the irreducible pentanomials. In this paper, we propose a new Repeated Polynomial(RP) for low-complexity bit-parallel multipliers over $F_{2^n}$. Also, three classes of Irreducible Repeated polynomials are considered which are denoted, respectively, by case 1, case 2 and case3. The proposed RP bit-parallel multiplier has lower complexities than ones based on pentanomials. If we consider finite fields that have neither a ESP nor a trinomial as an irreducible polynomial when $n\leq1,000$. Then, in Wu''s result, only 11 finite fields exist for three types of irreducible polynomials when $n\leq1,000$. However, in our result, there are 181, 232, and 443 finite fields of case 1, 2 and 3, respectively.