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http://dx.doi.org/10.13089/JKIISC.2010.20.5.11

Low Space Complexity Bit-Parallel Shifted Polynomial Basis Multipliers using Irreducible Trinomials  

Chang, Nam-Su (Sejong Cyber University)
Kim, Chang-Han (Semyung University)
Abstract
Recently, Fan and Dai introduced a Shifted Polynomial Basis and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. As the name implies, the SPB is obtained by multiplying the polynomial basis 1, ${\alpha}$, ${\cdots}$, ${\alpha}^{n-1}$ by ${\alpha}^{-\upsilon}$. Therefore, it is easy to transform the elements PB and SPB representations. After, based on the Modified Shifted Polynomial Basis(MSPB), SPB bit-parallel Mastrovito type I and type II multipliers for all irreducible trinomials are presented. In this paper, we present a bit-parallel architecture to multiply in SPB. This multiplier have a space complexity efficient than all previously presented architecture when n ${\neq}$ 2k. The proposed multiplier has more efficient space complexity than the best-result when 1 ${\leq}$ k ${\leq}$ (n+1)/3. Also, when (n+2)/3 ${\leq}$ k < n/2 the proposed multiplier has more efficient space complexity than the best-result except for some cases.
Keywords
Bit-Parallel Multiplier; Mastrovito Multiplier; Shifted Polynomial Basis; Irreducible Trinomial;
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Times Cited By KSCI : 1  (Citation Analysis)
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