• Proceedings of the Korea Multimedia Society Conference
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• 2001.11a
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• pp.699-702
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• 2001

본 논문에서는 비트 플래인 상에서 지역적인 복잡도를 이용하여 커버 이미지를 분할한 후 비밀 데이터를 삽입하는 스테가노그라피 방법을 연구하였다. 이 방법은 복잡도를 이용하여 비트 플래인 이미지를 informative 영역과 noise-like 영역으로 나누고, noise-like 영역에 데이터를 삽입한다. 삽입되는 데이터가 간단하다면 image conjugation을 적용하여 복잡한 형태로 만들어 커버 이미지에 삽입한다. 본 연구에서는 삽이 용량을 증가시키기 위해 복잡도를 모든 비트 플래인에 적용시키지 않고, 선택적으로 적용하여 46%의 최대 삽입용량과 화질의 증가를 얻을 수 있었다.

• The KIPS Transactions:PartB
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• v.9B no.1
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• pp.77-82
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• 2002

Progressive image transmission involves a progressive increase in the image resolution at the receiver from a lower to a higher resolution during the transmission of data. This is an effective way of using a limited transmission channel, because, after estimating the value of the data in the early transmission period, a decision can be made whether or not to proceed with the transmission of the remaining part. To realize more effective progressive image transmission, the current thesis divides an image into bit planes and then re-organizes each plane into a complementary quadtree structure. As a result, by transmitting the data on each bit plane and each level of the complementary quadtree in the appropriate order, the basic image contents can be understood with less data in the early period of transmission.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.799-801
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• 2001

Wong 은 디지털 영상의 인증과 무결성을 위해 해쉬 함수와 암호화 알고리즘을 공간 영역상에서 적용하였다. 본 논문에서는 웨이블릿 변환 영역 상에서 Wong 의 방법을 토대로 하여 fragile 워터마킹 방법을 제안한다. 즉, 삽입할 워터마크를 LSB 만 아니라 웨이블릿 계수의 비트 플래인을 고정시키지 않고 삽입함으로써, 워터마크의 삽입이 LSB에 고정되는 Wong 방법의 단점을 보완하였다. 실험결과 약간의 변형에도 영상의 변형 유무와 변형된 위치를 확인할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.753-760
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• 2012

This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of "01111110". When data bit stream consist of the consecutive 5-bit "1" after "0", the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits "1" after "0" in the input data stream, inserts violently the "0" after 5th "1" of the consecutive 5-bit "1" after "0". As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits "1" after "0" when the code is given to each characters.

• The Science & Technology
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• no.5 s.444
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• pp.42-44
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• 2006

"예쁜 그림 감상하듯 수학문제 풀었어요" - 황준묵 고등과학원 수학부 교수/ "신약개발로 생명 비밀 풀고파" - 김성훈 서울대학교 약학대학 교수/ "테라비트 낸드플래시도 가능할 것" - 황창규 삼성전자 반도체총괄 사장

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.67-80
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• 1998

논문에서는 프레임릴레이 프로토콜을 사용하는 암호 통신 시스템에 적합한 키 스트림 동기 방식을 제안하였다. 제안된 주소영역의 확장 비트를 이용한 키 스트림 동기 방식은 단위 측정 시간 동안 측정된 프레임릴레이 프로토콜의 주소영역의 확장 비트 정보와 플래그 패턴의 수신률을 이용하여 문턱값보다 적은 경우에 동기 신호와 세션 키를 전송하므로써 종래의 주기적인 동기 방식에서 전송 효율성 저하와 주기적인 상이한 세션 키 발생, 다음 주김까지 동기 이탈 상태로 인한 오류 확산 등의 단점을 해결하였다. 제안된 알고리즘을 데이터 링크 계층의 처리기능을 최소화하여 패킷 망의 고속화가 가능하도록 설계된 프레임릴레이 프로토콜에서 서비스되는 동기식 스트림 암호 통신 시스템에 적용하여 slip rate $10^{-7}$의 환경에서 주기가 Isec인 주기적인 동기 방식에서 요구되는 9.6*10/ sup 6/비트에 비해 6.4*$10^{5}$비트가 소요됨으로써 전송율 측면에서의 성능 향상과 오복호율과 오복호율과 오복호 데이터 비트 측면에서 성능 향상을 얻었다.다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.481-487
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• 2013

To successfully accomplish a bit synchronization, a synchronizer should exploit a preamble pattern. A MFM (modified frequency modulation) flag is uses as a preamble in a PJM (phase jitter modulation) mode RFID standard. In the recent work, a synchronizer for a PJM mode tag was proposed, which is composed of several correlators. In this paper, we present a new bit synchronizer in which a coarse synchronization is done as in the previous work while a fine synchronization is performed via exploiting a violation bit included in the MFM flag. We show that the proposed synchronizer can significantly reduce the overall hardware complexity at the expense of slight burden to a demodulator structure. Through simulation, we also show that its performance is comparable to that of the previous system despite its hardware simplicity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Korea Computer Industry Society
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• v.2 no.6
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• pp.791-802
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• 2001

In this paper, DARC(Data Radio Channel) error correction decoder for the U Subcarrier Broadcasting System is designed of using (272,190)$\times$(272,190) product code based on (272,190) shortened difference set cyclic code. This decoder has error flag of column and row direction that can store the result of the error correction of column and row direction in the block and frame structure, is designed to be of no benefit the output with majority logic determination to cancel the corrected and determined bit, and can improve by using the error correction method that no error correction of the row direction is performed, if error correction of the column direction is completely performed by error flag.