• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.635-646
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• 2011

In distributed video coding, low complexity encoder can be realized by shifting encoder-side complex processes to decoder-side. However, not only motion estimation/compensation processes but also complex LDPC decoding process are imposed to the Wyner-Ziv decoder, therefore decoder-side complexity has been one important issue to improve. LDPC decoding process consists of numerous iterative decoding processes, therefore complexity increases as the number of iteration increases. This iterative LDPC decoding process accounts for more than 60% of whole WZ decoding complexity, therefore it can be said to be a main target for complexity reduction. Previously, HDA (Hard Decision Aided) method is introduced for fast LDPC decoding process. For currently received parity bits, HDA method certainly reduces the complexity of decoding process, however, LDPC decoding process is still performed even with insufficient amount of parity request which cannot lead to successful LDPC decoding. Therefore, we can further reduce complexity by avoiding the decoding process for insufficient parity bits. In this paper, therefore, a parity request estimation method is proposed using bit plane-wise correlation and temporal correlation. Joint usage of HDA method and the proposed method achieves about 72% of complexity reduction in LDPC decoding process, while rate distortion performance is degraded only by -0.0275 dB in BDPSNR.

• The KIPS Transactions:PartB
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• v.11B no.6
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• pp.653-660
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• 2004

Object-oriented analysis-synthesis coding (OOASC) subdivides each image of a sequence into a number of moving objects and estimates and compensates the motion of each object. It employs a motion parameter technique for estimating motion information of each object. The motion parameter technique employing gradient operators requires a high computational load. The main objective of this paper is to present efficient motion parameter estimation techniques using the hierarchical structure in object-oriented analysis-synthesis coding. In order to achieve this goal, this paper proposes two algorithms : hybrid motion parameter estimation method (HMPEM) and adaptive motion parameter estimation method (AMPEM) using the hierarchical structure. HMPEM uses the proposed hierarchical structure, in which six or eight motion parameters are estimated by a parameter verification process in a low-resolution image, whose size is equal to one fourth of that of an original image. AMPEM uses the same hierarchical structure with the motion detection criterion that measures the amount of motion based on the temporal co-occurrence matrices for adaptive estimation of the motion parameters. This method is fast and easily implemented using parallel processing techniques. Theoretical analysis and computer simulation show that the peak signal to noise ratio (PSNR) of the image reconstructed by the proposed method lies between those of images reconstructed by the conventional 6- and 8-parameter estimation methods with a greatly reduced computational load by a factor of about four.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.902-910
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• 2016

Recently, the volume of mobile data traffic increases exponentially due to the emergence of various mobile services. In order to resolve the problem of mobile traffic increase, various new technologies have been devised. Especially, two-way relay communication in which two nodes can transfer data simultaneously through relay node, has gained lots of interests due to its capability to improve spectral efficiency. In this paper, we analyze the SM-PNC which combines Physical-layer Network Coding (PNC) and Spatial Modulation (SM) under two-way relay communication environment. Log-Likelihood Ratio (LLR) is considered and both separate decoding and direct decoding have been taken into account in performance analysis. Through performance evaluation, we have found that the bit error rate of the proposed scheme is improved compared to that of the conventional PNC scheme, especially when SNR is high and the number of antennas is large.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.30-43
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• 2008

Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.523-529
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• 2017

In this paper, we propose an efficient sphere decoding scheme that reduces computational complexity by combining receive and transmit ordering techniques in generalized spatial modulation systems, where the indexes of activated transmit antennas as well as the transmit symbols are exploited to transfer information to the receiver. In this scheme, the receive signals are optimally ordered so that the calculation for a candidate solution outside the sphere is terminated early to lower the computational complexity. In addition, the transmit ordering technique is applied to first search for candidate symbols and activated antennas having higher probabilities to further reduce the computational complexity. Simulation results show that the proposed doubly ordered sphere decoding scheme provides the same bit error rate performance with the conventional sphere decoding method and the sphere decoder employing only the receive ordering technique while it requires lower computational complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.106-115
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• 2003

Diverse multimedia services will be deployed at hand on 3G-and-beyond multi-service CDMA systems in order to satisfy different quality of service (QoS) according to traffic types. In order to use appropriate resources efficiently the call admission control (CAC) as a major resource control mechanism needs to be used to take care of efficient utilization of limited resources. In this paper, we propose a QoS-aware CAC (QCAC) that is enabled to provide service fairness and service differentiation in accordance with priority order and that applies the different thresholds in received power considering different QoS requirements such as different bit error rates (BER) when adopting total received power as the ceil load estimation. The proposed QCAC calculates the different thresholds of the different traffic types based on different required BER applies it for admission policy, and can get service fairness and differentiation in terms of call dropping probability as a main performance metric. The QCAC is aware of the QoS requirement per traffic type and allows admission discrimination according to traffic types in order to minimize the probability of QoS violation. Also the CAC needs to consider the resource allocation schemes such as complete sharing (CS), complete partitioning (CP), and priority sharing(PS) in order to provide fairness and service differentiation among traffic types. Among them, PS is closely related with the proposed QCAC having differently calculated threshold per each traffic type according to traffic priority orders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2181-2190
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• 1997

The synchronous stream cipher has the problem of synchronization loss by cycle slip. Synchronization loss make the state which sender and receiver can't communicate and it may make the receiving system disordered. To lessen the risk, we usually use a continuous resynchronization which achieve resynchronization at fixed timesteps by inserting synchronization pattern and session key. While we can get effectively resynchronizationby continuous resynchronization, there are some problems. In this paper, we proposed an adaptive resynchronization algorithm for cipher system using LAPB protocol. It is able to solve the problem of the continunous resynchronization.The proposed adaptive algorithm make resynchronization only in the case that the resynchronization is occurred by analyzing the address field of LAPB. It measure the receiving rate of the address field in the decesion duration. If the receiving rate is smaller than threshold value, it make resynchronization or not. By using adaptively resynchronization, it solves the problems of continunous resynchronization. When the proposed adaptive algorithm is applied to the synchronous stream cipher system which is used in X.25 packet network, it reduced the time for resynchronization by ten times. It means that 11.3% of total data for transmit is compressed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5A
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• pp.401-407
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• 2009

The multi-band (MB) ultra-wideband (UWB) communication system divides its available frequency spectrum in 3.1 to 10.6GHz into 16 sub-bands, which leads to inherent disparities between carrier frequencies of each sub-band. For instance, the highest carrier frequency is 2.65 times higher than the lowest one. Since the propagation loss is proportional to the square of the transmission frequency, the propagation loss on the sub-band having the highest carrier frequency is approximately 7 times larger than that on the sub-band having the lowest carrier frequency, which results in disparities between received signal powers on each sub-band. In this paper, we propose a novel correlation scheme for frequency hopping (FH) MB UWB communications, where the correlation time is adaptively adjusted relative to the sub-band, which reduces the disparity between the received signal energies on each sub-band. Such compensation for lower received powers on sub-bands having higher carrier frequency leads to an improvement on the total average bit error rate (BER) of the entire FH MB UWB communication system. We analyze the performance of the proposed correlation scheme in Nakagami fading channels, and it is shown that the performance gain provided by the proposed correlator is more significant as the Nakagami fading index n increases (i.e., better channel conditions).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.