• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.53-61
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• 2002

This paper proposes new DSP instructions and their architecture which efficiently implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecutre can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2Mbps data rate.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1627-1630
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• 2002

본 논문은 역추적 예견 알고리즘을 사용한 비터비 복호기에서의 TB단의 Polling 구조의 단순화 방법을 제시한다. 비터비 복호기의 3대 Unit중 하나인 Trace Back에서 역추적 예견 알고리즘을 사용할 경우 복호화 시점에서의 최소 State Metric 값을 찾아야 하는 번거로움을 줄일 수 있다. 하지만 복호 신호의 신뢰도 분산에 따라 Polling Unit 이 추가되어야 함에 따라 실제 하드웨어 복잡도에서의 이득은 미미한 것으로 알려져 있다. 제시된 구조에서는 Polling Unit을 단순화 할 수 있는 방법을 적용하였다. 기존 하드웨어와의 비교 평가를 위하여 IEEE802.11a의 표준에 따른 부호화율 1/2, 구속장 7을 갖는 비터비 디코더에 대하여 역추적 예견 알고리즘과 파이프라인 구조만을 갖는 경우와 제안된 단순화한 Polling Unit을 적용한 구조와의 비교에서 Trace Back Unit에서 약 45%의 감소 효과를 보였다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.234-237
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• 2003

본 논문은 이동 통신 및 IEEE 802.lla WLAN에서 사용하고 있는 컨벌루셔널 부호의 복호기인 비터비 복호기의 SMU(Survivor Metric Unit)의 최적 메모리 제어에 관한 연구이다. 비터비 복호기기 구조는 크게 BMU, ACSU, SMU부로 구성된다. 이때 SMU부는 최적의 경로를 역추적 하여 최종 복호 데이터를 출력해 주는 블록으로, 역추적 길이에 따라 메모리 사용 양과 복호 성능이 좌우된다. 따라서 본 논문에서는 최적 메모리 제어 알고리즘을 제안함으로써 복호 속도의 향상과 메모리 사용 양을 줄이는 방법을 제안한다. 제안 알고리즘의 성능을 검증하기 위해 기존의 비터비 복호기와 역추적 길이에 따른 비터비 복호기의 성능을 실험을 통해 분석함으로써 제안 방법의 객관적인 성능을 분석한다.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.190-196
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• 2004

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.45-52
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• 2004

This Paper presents a modified hard decision Viterbi decoder with an error prediction circuit enhancing performance for the burst error inputs. Viterbi decoder employs the maximum likelihood decoding algorithm which shows excellent error correction capability for the random error inputs. Viterbi decoders, however, suffer poor error correction performance for the burst error inputs under the fading channel. The proposed error prediction algorithm increases error correction capability for the burst errors. The algorithm estimaties the burst error data area using the maximum path metric for the erroneous inputs, It calculates burst error intervals based on increases in the maximum values of a path metric. The proposed decoder keeps a performance the same as the conventional decoders on AWGN channels for the IEEE802.l1a WLAN system. It shows performance inproving 15% on the burst error of multi-path fading channels, widely used in mobile systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.767-775
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• 2001

본 논문에서는 비터비 검출기의 복잡도와 전력소모를 감소시킬 수 있는 폴딩 비터비 검출기를 제안하였다. 제안된 폴딩 비터비 검출기는 상태 천이도가 대칭적인 것을 이용하여 상태는 서로 반전된 값을 갖는 것끼리 묶어지며, 확률거리의 경우 서로 부호가 반대인 값끼리 묶여진다. 제안된 폴딩 비터비 검출기를 EPRML 읽기 채널에 적용할 경우 확률거리 계산에 필요한 두 개의 가산기를 하나의 가감산기로 대체하여 기존의 GVA 알고리즘에 비해 하드웨어 복잡도를 37.4% 감소시킬 수 있었다. 또한 불필요한 전력소모의 원인이 되는 글리치 발생을 신호 재배치와 병렬 구조와 같은 상위 수준의 저전력 기법을 적용하여 억제한 결과 12.7%의 전력소모 감소를 나타내었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.646-649
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• 2011

Differential detection algorithm for DBO-CSS based on maximum signal energy detection (MSED) using viterbi algorithm is proposed. In order to mitigate SNR degradation caused by differential decoding, a modified viterbi algorithm with so called correlation metric (CM) in every state is proposed. It is shown that the performance gain of the proposed algorithm when compared with that of the conventional differential detection with the block decoding algorithm is about 2.5dB at BER = $10^{-5}$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.3
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• pp.9-18
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• 2001

In this paper, we present the joint symbol detection and channel estimation for an orthogonal frequency division multiplexing (OFDM) system in fading channels. The proposed methods are based on decision-directed channel estimation (DDCE) method and their symbol detection is achieved by using Viterbi algorithm. This Viterbi decision-directed channel estimation (VDDCE) method tracks time-varying channels and detects a maximum likelihood symbol sequence. Recursive Viterbi decision-directed channel estimation (RVDDCE) method based on VDDCE method is proposed to shorten the detecting depth. In this method, channel estimate and Viterbi processing are recursively performed every interval of training symbol. Also, average chann'el estimation (ACE) technique to reduce the effect of additive white Gaussian noise (AWGN) is applied VDDCE method and RVDDCE method. These proposed methods arc demonstrated by computer simulation.