• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.767-775
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• 2001

본 논문에서는 비터비 검출기의 복잡도와 전력소모를 감소시킬 수 있는 폴딩 비터비 검출기를 제안하였다. 제안된 폴딩 비터비 검출기는 상태 천이도가 대칭적인 것을 이용하여 상태는 서로 반전된 값을 갖는 것끼리 묶어지며, 확률거리의 경우 서로 부호가 반대인 값끼리 묶여진다. 제안된 폴딩 비터비 검출기를 EPRML 읽기 채널에 적용할 경우 확률거리 계산에 필요한 두 개의 가산기를 하나의 가감산기로 대체하여 기존의 GVA 알고리즘에 비해 하드웨어 복잡도를 37.4% 감소시킬 수 있었다. 또한 불필요한 전력소모의 원인이 되는 글리치 발생을 신호 재배치와 병렬 구조와 같은 상위 수준의 저전력 기법을 적용하여 억제한 결과 12.7%의 전력소모 감소를 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.1-8
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• 2004

Viterbi decoders are widely used for communication and high-density storage devices. An add-compare-select(ACS) unit has been an active research area for a long time because it is the most critical component in determining the operation speed and power-consumption of the Viterbi decoder. We propose a new comparator which is faster and consumes less power than existing ones. We also used the new comparator for a Viterbi decoder and our simulations results show the Viterbi decoder outperforms existing ones at least $20\%$ in its operating speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.827-832
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• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.583-586
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• 2004

Transition jitter noise is one of major sources of detection errors in high density recording channels. Implementation complexity of the optimal detector for such channels is high due to the data dependency and correlated nature of the jitter noise. In this paper, two types of hardware efficient sub-optimal detectors are derived by modifying branch metric of Viterbi algorithm and applied to partial response (PR) channels combined with run length limited modulation coding. The additional complexity over the conventional Viterbi algorithm to incorporate the modified branch metric is either a multiplication or an addition for each branch metric in the Viterbi trellis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.891-897
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• 2003

Partial response maxim likelihood (PRML) is a powerful and indispensable detection scheme for perpendicular magnetic recording channels. The performance of PRML can be improved by incorporating a noise prediction scheme into branch metric computations of Viterbi algorithm (VA). However, the systems constructed by VA have shortcomings in the form of high complexity and cost. In this connection, a new simple detection scheme is proposed by exploiting the minimum run-length parameter d=1 of RLL code. The proposed detection scheme have a slicer instead of Viterbi detector and a noise predictor as a feedback filter. Therefore, to improve BER performance, the proposed detection scheme is extended to dual detection scheme for improving the BER performance. Simulation results show that the proposed scheme has a comparable performance to noise-predictive maximum likelihood (NPML) detector with less complexity when the partial response (PR) target is (1,2,1).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.927-932
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• 2006

We Propose a partial response maximum likelihood(PRML) detection method that improves the performance of the high-density optical storage system. It concurrently adjusts the coefficient of equalizer and reference values of branches in Viterbi detector. For the estimation of asymmetric channel characteristics by the tangential tilt, we exploit sync patterns in each data frame. The simulation result shows it improves the Performance up to 4dB at 10-6 BER compared to conventional adaptive PRML.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9C
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• pp.871-876
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• 2005

In this paper, we propose an improved partial response maximum likelihood (PRML) detection scheme that has an adaptive equalizer and can be applied in the asymmetric optical recording system with high-density. We confirmed that the proposed PRML detector improves detection performance. In addition, we implemented the detector by Verilog HDL. The adaptive equalizer is composed of tap coefficient updating unit using LMS algorithn and FIR filter. FIR filter is implemented by the transposed direct form architecture for high speed operation. Viterbi detector is implemented by the register exchange method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1445-1452
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• 2000

In general, the communication channel can be modeled as inter-symbol interference(ISI) and additive white gaussian noise channel. Viterbi algorithm is optimum detector for transmitted data at transmitter, but it needs large computational complexity. For the sake of this problem, adaptive equalizers are employed for channel equalization which is not attractive for mixed phase channel. In this paper, we propose the effective new channel equalizer for mixed phase channel and show the better performance than previous equalizers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1548-1557
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• 1994

In this paper, the dual mode error correcting adaptive decoding algorithm which is adapted to the continuous phase frequency shift keying(CPFSK) modulation is presented as a technique for overcoming the distortion that reveals from the Rayleigh fading channel. The dual mode adaptive decoder nominally operates as a Viterbi decoder and switches to the burst error correcting mode, whenever the decoder detects an uncorrectable burst error pattern. Under the fading channel environment and when the usable memory quantity is restricted, the dual mode adaptive decoding algorithm shows an advantage in the BER performance over the interleaving technique, and also obtains the merit of not needing the large time delay that the interleaving technique requires. The experimental results from the computer simulation demonstrate the performance of the algorithm and verify the theoretical results.