• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.128-138
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• 2010

In this paper, we propose a new bit assignment scheme for Wyner-Ziv video coding. Distributed video coding (DVC) is a new video coding paradigm which enables greatly low complexity encoding because it does not have any motion prediction module at encoder. Therefore, it is very well suited for many applications such as video communication, video surveillance, extremely low power consumption video coding, and other portable applications. Theoretically, the Wyner-Ziv video coding is proved to achieve the same rate-distortion (RD) performance comparable to that of the joint video coding. However, its RD performance has much gap compared to MC-DCT-based video coding such as H.264/AVC. Moreover, Transform Domain Wyner-Ziv (TDWZ) video coding which is a kind of DVC with transform module has difficulty of exact bit assignment because the entire image is treated as a same message. In this paper, we propose a feasible bit assignment algorithm using adaptive quantization matrix selection for the TDWZ video coding. The proposed method can calculate suitable bit amount for each region using the local characteristics of image. Simulation results show that the proposed method can enhance coding performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.4
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• pp.195-205
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• 2014

The ultra-high definition television (UHDTV) has been considered as a next generation broadcsating service. However the conventional digital terrestrial transmission system cannot afford the required transmission data rate of UHDTV, and thus adopting ultra-high order constellation, such as 4096-QAM, into the conventional DTT systems has been studied. In particular, when the ultra-high order constellation is adopted into the digital video broadcasting-2nd generation terrestrial (DVB-T2) unequal-error protection (UEP) properties of a codeword of an error correction coding and ultra-high order constellations should be properly matched by bit mapper in order to enhance the decoding performance. Because long codeword results in a heavy computational complexity to design the bit mapper, the DVB-T2 divided it into cascaded blocks, the bit interleaver and the bit-to-cell DEMUX, and there have been many researches related to each block. However, there are few published study related to design methodology of bit interleaver. In this respect, this paper proposes a design methodology of the bit interleaver and presents bit interleavers of 1024-QAM and 4096-QAM according to the proposed design algorithm. The newly designed interleavers improved the decoding performance of the error correction coding by maximally 0.6 dB SNR over both of AWGN and random fading channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.939-947
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• 2010

The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.413-421
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• 2005

As the population of HDTV is growing, among many useful features of modern set top boxes (STBs) or digital video recorders (DVRs), video browsing, visual bookmark, and picture-in-picture capabilities are very frequently required. These features typically employ reduced-size versions of video frames, or thumbnail images. Most thumbnail generation approaches generate DC images directly from a compressed video stream. A discrete cosine transform (DCT) coefficient for which the frequency is zero in both dimensions in a compressed block is called a DC coefficient and is simply used to construct a DC image. If a block has been encoded with field DCT, a few AC coefficients are needed to generate the DC image in addition to a DC coefficient. However, the bit length of a codeword coded with variable length coding (VLC) cannot be determined until the previous VLC codeword has been decoded, thus it is required that all codewords should be fully decoded regardless of their necessary for DC image generation. In this paper, we propose a method especially for fast DC image generation from an I-frame using multiple-symbol lookup table (mLUT). The experimental results show that the method using the mLUT improves the performance greatly by reducing LUT count by 50$\%$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.258-268
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• 2001

The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3％ for structure I and 30.7％ for structure II. The memory is proved to reduce 31.3％ for structure I and II.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.39-48
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• 2004

Turbo codes, whose performance in bit error rate is close to the Shannon limit, have been adopted as a part of standard for the third-generation high-speed wireless data services. Iterative Turbo decoding results in decoding delay and high power consumption. As wireless communication systems can only use limited power supply, low power design techniques are essential for mobile device implementation. This paper proposes new effective criteria for stopping the iteration process in turbo decoding to reduce power consumption. By setting two stopping criteria, decodable threshold and undecodable threshold, we can effectively reduce the number of decoding iterations with only negligible error-correcting performance degradation. Simulation results show that the number of unsuccessful error-correction can be reduced by 89% and the number of decoding iterations can be reduced by 29% on the average among 12500 simulations when compared with those of an existing typical method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.22-28
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• 2007

High PAPR (peak-to-average power ratio) is a major drawback of OFDM (orthogonal frequency division multiplexing) signals. In this paper, a modified SLM (selective mapping) technique that uses erasure decoding of RS (Reed-Solomon) codes is presented. At the transmitter a set of phase sequences are multiplied such that some portions of check symbols in RS-coded OFDM data blocks are phase-rotated. At the receiver, RS decoding is performed with the phase-rotated check symbols being treated as erasures. Hence, there is no need to send side information about the phase sequence selected to transmit for the lowest PAPR. In addition, the estimation process for the selected phase sequence is no longer needed at the receiver, leading to improvement in terms of complexity and performance. To evaluate the performance of this technique, the CCDF (complementary cumulative distribution function) of PAPR, the BER (bit error rate) and the decoding failure probability are compared with those of the previous SLM techniques.