• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.701-704
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• 2001

본 논문은 영상압축 표준의 하나로 표준화가 진행중 인 H.26L에 효율적인 저전력 움직임 추정 구조를 제안한다. 제안하는 방식은 움직임 추정에 사용하는 이전 프레임에서의 움직임 벡터 발생 빈도와 경향을 이용하여 계산량과 수행시간을 줄인다. 그리고 가변 블럭 정합을 고려하여 먼저 최소 블럭 크기 단위로 블럭 SAD를 계산한 후 다른 모드 블럭 SAD 를 계산으로 생성한다. 제안하는 방식은 기존의 저전력 블럭 정합 방식과 비교하여 최대 31% 전력 소모 감소가 이루어지며 완전 전역 탐색 블럭 정합 방식에 비해 평균 75-90%의 계산량이 감소된다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2768-2775
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• 1996

VariableBlock Matching algorithm is effective for the estimation of motion vector at complexor edge region by means of using variable block size with respect to the image block. But since VBM algorithm requires considerable number of operations, to solve this problem, we present an algorithm which uses difference images and quad tree structure, and estimates motion using various fast block matching algorithms.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.6
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• pp.692-702
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• 2001

In this paper, a new block-matching algorithm for standard video encoder is proposed. The algorithm finds a motion vector using the increasing SAD transition curve for each predefined candidates, not a coarse-to-fine approach as a conventional method. To remove low-probability candidates at the early stage of accumulation, a dispersed accumulation matrix is also proposed. This matrix guarantees high-linearity to the SAD transition curve. Therefore, base on this method, we present a new fast block-matching algorithm with the slice competition technique. The Candidate Selection Step and the Candidate Competition Step makes an out-performance model that considerably reduces computational power and not to be trapped into local minima. The computational power is reduced by 10%~70% than that of the conventional BMAs. Regarding computational time, an 18%~35% reduction was achieved by the proposed algorithm. Finally, the average MAD is always low in various bit-streams. The results were also very similar to the MAD of the full search block-matching algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1925-1938
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• 2001

In this paper, a new block-matching algorithm for standard video encoder is presented. The slice competition method is proposed as a new scheme, as opposed to a coarse-to-fine approach. The order of calculating the SAD(Sum of Absolute Difference) to fad the best matching block is changed from a raster order to a dispersed one. Based on this scheme, the increasing SAD curve during its calculation is more linear than that of other curves. Then, the candidates of low probability can be removed in the early stage of calculation. And new MV prediction technique with an adaptive search range scheme also assists the proposed block-matching algorithm. As a result, an average of 13% improvement in computational power is recorded by only the proposed MV prediction technique. Synthetically, the computational power is reduced by 3977∼77% than that of the conventional BMAs. The average MAD is always low in various sequences. The results are also very close to the MAD of the full search block-matching algorithm.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.12
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• pp.63-68
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• 1998

We present a fast adaptive block matching algorithm using characteristic of the motion vector distribution. In the presented method, the block is classified into one of four motion categories: stationary block, quasi-stationary block, medium-motion block or high-motion block according to characteristic of the MAD(0,0) distribution for motion vector, each block estiamtes the motion vector adaptively. By the simulation, the PSNR of our algorithm is similar to NTSS method. The computation amount of the presented method decreased 30.44% ~ 40.27% more than NTSS method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.543-550
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• 2000

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.503-509
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• 2007

Low-power motion estimation is required for video coding in portable information devices. In this paper, we propose a low-power motion estimation algorithm and 1-D systolic may VLSI architecture using full search block matching algorithm (FSBMA). Main power dissipation sources of FSBMA are complex computations and frequent memory accesses for data in the search area. In the proposed algorithm, memory accesses and computations are reduced by using 1D PE (processing array) array architecture performing motion estimation of two neighboring blocks in parallel and by skipping unnecessary computations during motion estimation. The VLSI implementation results of the algorithm show that the proposed VLSI architecture can save 9.3% power dissipation and can operate two times faster than an existing low-power motion estimator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2783-2797
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• 1997

This paper proposes a new motion estimation algorithm that employs matching in a variable search area. Instead of uisg a fixed search range for coarse motion estimation, we examine a varying search range, which is determined adaptively by the peak signal to noise ratio (PSNR) of the frame difference. The hexagonal matching method is one of the refined methods in image warping. It produces improved image quality, but it requires a large amount of computataions. The proposed adaptive partial matching method reduces computational complexity below about 50% of the hexagonal matching method, while maintaining the image quality comparable. The performance of two motion compensation methods, which combine the affine or bilinear transformation with the proposed motion estimation algorithm, is evaluated based on the following criteria:computtational complexity, number of coding bits, and reconstructed image quality. The quality of reconstructed images by the proposed method is substantially improved relative to the conventional BMA method, and is comparable to the full hexagonal matching method;in addition, computational complexity and the number of coding bits are reduced significantly.