• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.2
• /
• pp.526-533
• /
• 1996

In this paper, the 800 MHz band N fractional frquency synthesizer having 677 channel with 30 kHz channel bandwidth is designed on the based on the theory which is dervied in terms of the relation between reference freqiency and the number of channels, loop bandwidth and acquistion time. The experimental resuls show 10 Hz deviation from the bandwidth and acquisition time. The experimental results show 10 Hz deviation from the bandwidth, the spurious suppression of aroud -45 dBc and the acqusition time of 1.44 ms. The results satisfy the given specification, but don't achieve thebesired spurious -60 dBc suppression. It is found that 500 hop per second will be possible over the range from 800 to 820 MHz.

• The Mathematical Education
• /
• v.12 no.2
• /
• pp.5-12
• /
• 1974

단위원을 가지는 하환환에 있어서의 Prime Spectrum에 관하여 다음 세가지 사실을 증명하였다. 1. X를 환 R의 prime spectrum, C(X)를 X에서 정의되는 실연적함수의 환, X를 C(X)의 maximal spectrum이라 하면 X는 C(X)의 prime spectrum의 부분공간으로서의 한 T-space로 된다. N을 환 R의 nilradical이라 하면, R/N이 regula 이면 X와 X는 위상동형이다. 2. f: R$\longrightarrow$R'을 ring homomorphism, P를 R의 한 Prime ideal, $R_{p}$, R'$_{p}$를 각각 S=R-P 및 f(S)에 관한 분수환(ring of fraction)이라 하고, k(P)를 local ring $R_{p}$의 residue' field라 할 때, R'의 prime spectrum의 부분공간인 $f^{*-1}$(P)는 k(P)(equation omitted)$_{R}$R'의 prime spectrum과 위상동형이다. 단 f*는 f*(Q)=$f^{-1}$(Q)로서 정의되는 함수 s*:Spec(R')$\longrightarrow$Spec(R)이다. 3. X를 환 S의 prime spectrum, N을 R의 nilradical이라 할 때, 다음 네가지 사실은 동치이다. (1) R/N 은 regular 이다. (2) X는 Zarski topology에 관하여 Hausdorff 공간이다. (3) X에서의 Zarski topology와 constructible topology와는 일치한다. (4) R의 임의의 원소 f에 대하여 f를 포함하지 않는 R의 prime ideal 전체의 집합 $X_{f}$는 Zarski topology에 관하여 개집합인 동시에 폐집합이다.폐집합이다....

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.1158-1162
• /
• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.8 no.1
• /
• pp.147-155
• /
• 2012

Fountain codes ensure reliability and robustness for time varying channels in wireless communication. In this paper, the concatenated fountain codes for AWGN and slow fading channels are investigated. Wireless system model, which includes the concatenated fountain code and modulation, is proposed. Maximum achievable rate is used for analyzing the performance of the system model for AWGN and fading channels. Belief Propagation (BP) algorithm is used for exploiting the soft information received at the decoder. Simulation results show that, concatenated fountain codes performs significantly better than that of a conventional Fountain codes with large packet lengths for higher Signal to Noise Ratio (SNR) in slow fading channels.

• Applied Biological Chemistry
• /
• v.23 no.1
• /
• pp.1-6
• /
• 1980

The sorption characteristics of red pepper powder were analyzed in respect to its storing humidities and the types of powder product. The sorption rate of the powder was affected by the humidity values under which it was stored. At low relative humidity values below 70% RH the sorption equilibrium was easily attained, but at the higher humidity over 75% RH the equilibrium state was not reached even after a long period of storage. From the estimation of the sorption rate at arbitrary humidity an empirical equation was obtained; In ${\frac{dw}{dt}}=n\;ln(t)+ln\;c$, where w is moisture content(%) absorbed, t is time (hour) and n and c are empirical constants which were determined from empirical data. Particle sizes and drying methods of red pepper showed little effect on the sorption behavior.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.32-38
• /
• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.49-54
• /
• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.45 no.6
• /
• pp.87-93
• /
• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.5
• /
• pp.29-34
• /
• 2014

We introduce a number of antenna optimization problem for the zero-forcing beamforming (ZFBF) scheme to enhance energy-efficiency (EE) of the multiple-input-multiple-output broadcast channel. For proposed optimization problem, we assume an instantaneous channel gain of the ZFBF scheme as an average channel gain, given by $N_a-K+1$, in order to reduce a computational complexity of finding the number of active antennas $N_a$. Then, we convert a fractional-form objective function into a subtractive-form, and find a solution of $N_a$ and the maximum EE by an iterative process. Simulation results show that the maximum EE value obtained by proposed algorithm is almost identical to the optimal EE value by the exhaustive search method.

• Korean Journal of Ecology and Environment
• /
• v.43 no.2
• /
• pp.263-270
• /
• 2010

This is a research on development of water purification equipment called artificial floating island (=AFI) for the stagnant water area which can secure exuberant landscape and water-friendility. The equipment devised in this study is designed to make up the weakness of conventional AFIs and improves the removal efficiency of pollutants using the mixture of media and plants. The air compressor positioned at the inlet releases air with inflow continuously, the water pump at the outlet sprays as a form of fountain with causing a disturbance on stable water column, then, both of them contribute improvement of water quality over a large area. We applied Bio-stone as a media in this system and performed an experiment of pre-efficiency test, and we concluded that the higher pollutants concentration of inflow, the higher removal efficiency we obtained. At the result of lab-scale experiment, in the case of high-concentration inflow, in the removal efficiency of SS is 62.2%, BOD is 50.2%, COD is 55.1%, T-N is 31.6%, T-P is 38.4%. In addition, to evaluate the field application, we set up the facilities in Sin-gal lake located in Yongin-Si Gyeonggi-Do, and researched on the removal efficiency of outflow relative to the inflow. As a result, SS is 53.5%, BOD is 32.8%, COD is 36.9%, T-N is 22.6%, T-N is 33.2%.