• Title/Summary/Keyword: 분석 칩

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Paper-Based Neuraminidase Assay Sensor for Detection of Influenza Viruses (인플루엔자 바이러스 검출을 위한 종이 기반 neuraminidase 효소 활성 평가 센서 개발)

  • Hwang, Cheol-hwan;Jeong, Seong-Geun;Park, Han-Kyu;Lee, Chang-Soo;Kim, Yun-Gon
    • Korean Chemical Engineering Research
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    • v.54 no.3
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    • pp.380-386
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    • 2016
  • In this study, we described a paper-based neuraminidase assay sensor (PNAS) which can be applied to detect the infection by influenza viruses. The PNAS was designed and manufactured to quantitatively identify the levels of neuraminidase in the sample, which is based on colorimetric analysis using the X-Neu5Ac substrate. The limit of detection of the PNAS was determined as 0.004 U/mL of neuraminidase. According to the amount of neuraminidase in human serum, the PNAS could monitor the enzyme activity with a good linearity ($R^2$ > 0.99). In addition, the initial performance of the PNAS has been maintained up to 70 days in the $4^{\circ}C$. Finally, we demonstrated whether the Michaelis-Menten kinetics is applied to the PNAS, which can show the reliability of the enzyme reactions. The kinetic studies indicated that the PNAS provides the good condition for enzyme reactions ($K_m=8.327{\times}10^{-3}M$), but they were performed on paper chip nonetheless. The paper-based neuraminidase assay sensor may be useful in a wide range of rapid and safe detection of influenza virus.

Estimation of the steps of cardiovascular disease by machine learning based on aptamers-based biochip data (기계학습에 의한 압타머칩 데이터 기반 심혈관 질환 단계의 예측)

  • Kim Byoung-Hee;Kim Sung-Chun;Zhang Byoung-Tak
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.06a
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    • pp.85-87
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    • 2006
  • 압타머칩은 (주)제노프라에서 개발한 새로운 개념의 바이오칩으로서, 압타머(aptamer)를 이용하여 혈액중의 특정 단백질군의 상대적인 양의 변화를 측정할 수 있으며, 질병 진단에 바로 응용할 수 있는 도구이다. 본 논문에서는 압타머칩 데이터 분석을 통해 심혈관 질환 환자의 질병 진행 단계를 예측할 수 있음을 보인다. 정상, 안정/불안정성 협심증, 심근경색의 네 단계로 표지된 환자의 혈액 샘플로부터 제작한 (주)제노프라의 3K 압타머칩 데이터를, 일반 DNA 마이크로어레이 분석과 동일한 과정을 거쳐 분류한 결과, 각 단계별 환자샘플이 확연히 구분되는 것을 확인하였다. 분산분석 결과 P-Value를 이용하여 자질 선택을 수행하고, 분류 알고리즘으로는 신경망, 결정트리, SVM, 베이지안망을 적용한 결과. 각 알고리즘별로 50대 남성환자 31개의 샘플에 대하여 $77{\sim}100%$의 정확도로 심혈관 질환의 단계를 구분해내었다.

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Design of Lung Sound Analyzer Using Adaptive Digital Filter and DSP Chip (적응 디지탈 필터와 DSP 칩을 이용한 폐음 분석기 설계)

  • 김규한;조일준
    • Journal of Biomedical Engineering Research
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    • v.10 no.2
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    • pp.151-156
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    • 1989
  • Lung sound analyer which can provide an objective diagnosis of patients with pulmonary and bronchial disorders is designed. For the purpose of power spectrum analysis, adaptive digital filtering technique and TM - S320C25 DSP chip is used. As a results, adaptive lattice Wiener filter could eliminate heart sounds with a few of 10th order and on the distribution of power spectrum each patterns has shown in normal vescicular breathy from 100 Hz to 200 Hz, in crackle sound from 100 Hz to 400 Hz, in wheeze sound from 150 Hz to 600 Hz.

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Analysis of Technology for RF Radiated E/H Fields EMS Tests (복사 전기장 및 자기장 내성시험 기술 분석)

  • Yum, J.H.;Choi, H.D.;Chae, J.S.
    • Electronics and Telecommunications Trends
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    • v.17 no.4 s.76
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    • pp.123-134
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    • 2002
  • ISO/IEC14443-1(1), ISO/IEC10536-1(2), 그리고 ISO/IEC15693-1(3)에서 정의하고 있는 비접촉식 카드의 교류전기장 및 교류자기장에 대한 내성력 시험에 대해 살펴보고자 한다. 상기 규격은 ISO/IEC JTC1 기술위원회의 SC17에서 다루고 있으며, 아직 상기 표준 규격은 초안 상태에 있어 상세한 시험 방법에 대한 규격이 마련되어 있지 않은 실정이다. 그럼에도 불구하고 칩 카드 수입국은 수출업자에게 교류전기장 및 교류자기장 내성시험을 요구하고 있다. 따라서 업계에서는 시험 시설, 시험 방법, 시험 절차, 시험 평가 부분에서 많은 혼란이 발생되고 있다. 이러한 시험에 대한 대응책이 국가적 차원에서 시급히 마련되어야 할 것이다. 본 고에서는 이를 위한 일련의 과정으로서, 칩 카드 관련 국제 규격(1)-(5) 동향을 살펴보고, 교류전기장 및 교류자기장 내성력 시험 절차를 마련하기 위한 관점에서 IEC61000 시리즈 중에서 RF 복사 내성시험인 IEC61000-4-3(6), IEC61000-4-8, IEC61000-4-9, IEC61000-4-10, IEC61000-4-23(7)에 대한 분석을 동시에 실시하였다.

Comparison of Efficiency for Wood Fuels (Chips and Pellets) by Life Cycle Assessment (LCA 접근방법에 의한 목질연료(칩, 펠릿)의 효율성 비교)

  • Choi, Young-Seop;Kim, Joon-Soon;Cha, Du-Song
    • Journal of Korean Society of Forest Science
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    • v.98 no.4
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    • pp.426-434
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    • 2009
  • This study was carried out to derive the most optimal production process for the wood fuels(chip and pellet), by collecting cost data on each procedure through the life cycle assessment approach, and to compare between the profitability and efficiency, from the view points of producers and consumers, irrespectively. The costs accounted in this analysis were based on the opportunity cost. The results show that wood chips are cheaper than wood pellets in production costs. In respect to the process with the lowest production cost, while wood chips should be to crush collected residues into pieces on the spot for merchandizing, wood pellets need to be transported to manufactory for pelletizing. The study findings also include that the profits, which is estimated by subtracting expenses from gained sale revenue, were a bit higher for wood chips than wood pellets. Additionally, the price ratio of wood pellets to wood chips for getting the same caloric value appears to be 1.27. Despite of economic benefits of processing wood chips, there are several problems in practice. For producers, there is a possible increase in not only transportation cost for conveying crushers to the dispersed places, but storage cost due to the lack of the marketplaces in the immediate surroundings. For consumers, on the other hand, there are some challenging issues, such as bulky storage facility requirement, additional labor for fuel supplement, frequent ashes disposal, and decomposition in summer and freezing in winter caused by wood chips' own moisture.

Layout-Based Inductance Model for On-Chip Power Distribution Grid Structures (레이아웃 기반 온-칩 전력 분배 격자 구조의 인덕턴스 모델 개발 및 적용)

  • Jo, JeongMin;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.9
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    • pp.259-269
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    • 2012
  • With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

Microstructural Charicteristics of Pb-free Solder Joints (무연솔더 접합부의 미세조직 특성)

  • Yu, A-Mi;Jang, Jae-Won;Kim, Mok-Soon;Lee, Jong-Hyun;Kim, Jun-Ki
    • Proceedings of the KWS Conference
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    • 2010.05a
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    • pp.82-82
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    • 2010
  • 표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

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Production and Fuel Properties of Wood Chips from Logging Residues by Timber Harvesting Methods (목재수확 방법에 따른 벌채부산물 목재칩의 생산 및 연료 특성)

  • Choi, Yun-Sung;Jeong, In-Seon;Cho, Min-Jae;Mun, Ho-Seong;Oh, Jae-Heun
    • Journal of Korean Society of Forest Science
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    • v.110 no.2
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    • pp.217-232
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    • 2021
  • This study calculated the productivity and cost of extraction and processing of logging residues by cut-to-length (CTL) and whole-tree (WT) harvesting methods. In addition, the comparative analysis of the characteristics of wood chip fuel to examine whether it was suitable for the fuel conditions of the energy facility. In the harvesting and processing system to produce the wood chips of logging residues the system productivity and cost of the CTL harvesting system were 1.6 Gwt/SMH and 89,865 won/Gwt, respectively. The productivity and cost of the WT harvesting system were 2.9 Gwt/SMH and 72,974 won/Gwt, respectively. The WT harvesting productivity increased 1.3times while harvesting cost decreased by 18.7% compared to the CTL harvesting system. The logging residues of wood chips were not suitable for CTL wood chips based on International Organization for Standardization (ISO 17225-4:2021) and South Korea standard (NIFoS, 2020), but the quality (A2, Second class) was improved through screening operation. The WT-unscreened wood chips conformed to NIFoS standard (second class) and did not conform to ISO but were improved through screening operation (Second class). In addition to the energy facility in plant A, all wood chips except CTL-unscreened wood chips were available through drying processing. The WT-unscreened wood chips were the lowest at 99,408 won/Gwt. Plants B, C, and D had higher moisture content than plant A, so WT-unscreened wood chips without drying processing were the lowest at 57,204 won/Gwt. Therefore, the production of logging residues should improve with operation methods that improve the quality of wood chips required for applying the variable biomass and energy facility.

Evaluation of Solder Printing Efficiency with the Variation of Stencil Aperture Size (스텐실 개구홀 크기 변화에 따른 솔더프린팅 인쇄효율 평가)

  • Kwon, Sang-Hyun;Kim, Jeong-Han;Lee, Chang-Woo;Yoo, Se-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.4
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    • pp.71-77
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    • 2011
  • Main parameters of the screen printing were determined and the printing parameters were optimized for 0402, 0603, and 1005 chips in this study. The solder pastes used in this study were Sn-3.0Ag-0.5Cu and Sn-0.7Cu. The process parameters were stencil thickness, squeegee angle, printing speed, stencil separating speed and gap between stencil and PCB. The printing pressure was fixed at 2 $kgf/cm^2$. From ANOVA results, the stencil thickness and the squeegee angle were determined to be main parameters for the printing efficiency. The printing efficiency was optimized with varying two main parameters, the stencil thickness and the squeegee angle. The printing efficiency increased as the squeegee angle was lowered under 45o for all chips. For the 0402 and the 0603 chips, the printing efficiency increased as the stencil thickness decreased. On the other hand, for the 1005 chip, the printing efficiency increased as the stencil thickness increased.