• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3715-3722
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.473-480
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• 2006

Extraction is tile most important step in global minimization. Its approache is to identify and extract subexpressions, which are multiple-cubes or single-cubes, common to two or more expressions which can be used to reduce the total number of literals in a Boolean network. Extraction is described as either algebraic or Boolean according to the trade-off between run-time and optimization. Boolean extraction is capable of providing better results, but difficulty in finding common Boolean divisors arises. In this paper, we present a new method for Boolean extraction to remove the difficulty. The key idea is to identify and extract two-cube Boolean subexpression pairs from each expression in a Boolean network. Experimental results show the improvements in the literal counts over the extraction in SIS for some benchmark circuits.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.43-49
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• 2012

Personalized message syndication is an important process for maximizing the effect of mobile marketing. This paper proposes an algorithm for determining clients satisfying target conditions in real-time. The proxy server as an intermediate node stores client profiles (gender, age, location, etc) and their respective summaries into a database. When a company syndicates messages at run time, the proxy server maps target conditions expressed by boolean expressions to integer value and determines target clients by comparing target value with profile summary. Thus, this approach provides efficient personalized message syndication in very large systems with millions of clients because it can determine target clients in real-time and work with a traditional database easily.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.1-6
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• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11
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• pp.3544-3555
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• 2000

매칭방법은 기하 및 입체 모델링에서 재단 곡면과 이들에 대한 부울 연산에 사용되는 기초적인 연산이다. 그러나 매칭연산은 부드러움을 정확하게 표현하는데 고 차수의 미분계수 제약조건으로 인하여 많은 계산량이 필요할 뿐만 아니라 곡면상의 여러 점을 동시에 선택하여 이동하였을 때, 곡면표현에 사용되는 복잡한 함수식으로 인하여 일반해를 구하기 어려운 단점을 가진다. 본 논문은 분수식에 의하여 RMC(Rotation-Minimizing Curve)을 정의하고 이를 이용하여 자유 형태 곡면간에 변형 매칭 방법을 제안한다. RMC는 매칭곡선과 곡면의 접선벡터, 회전벡터, 곡률의 변화율과 같은 기하학적 기법을 기반으로 한다. 제안한 방법은 입력으로 주어지는 곡면의 기하학적 복잡도와는 무관하게 매칭을 수행할 수 있으며 수행 성능은 계산된 매칭 곡선의 복잡도에 의해서만 좌우된다. 또한 곡선 표현에 사용된 값들을 정의된 매칭 곡선식에 그대로 적용할 수 있었으므로 최적화 응용 문제에 효율적으로 적용할 수 있다.

• The Journal of Korean Association of Computer Education
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• v.20 no.4
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• pp.77-84
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• 2017

This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.17-27
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• 2000

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function. and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to build an extended co-kernel cube matrix using co-kernel/kernel pairs and kernel/kernel pairs together. The extended co-kernel cube matrix makes it possible to yield a Boolean factored form. We also propose a heuristic method for covering of the extended co-kernel cube matrix. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Brayton's co-kernel cube matrix.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.652-657
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• 2013

In this paper the design methode of a separated composition state machine based on the compositive map with two chaotic maps together and the result of that is proposed. The digital circuits of chaotic composition map for the use of chaotic binary stream generator are designed in this work. The discretized truth table of chaotic composition function which is composed of two chaotic functions - the saw tooth function and skewed logistic function - is made out, and also simplefied Boolean algebras of digital circuits are obtained as a mathematical model. Consequently, the digital circuits of the map for chaotic composition function are presented in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.