• The Journal of Korean Association of Computer Education
• /
• v.15 no.1
• /
• pp.65-72
• /
• 2012

Generally, a logic function has many factored forms. The problem of finding more compact factored form is one of the basic operations in logic synthesis. In this paper, we present a new method for factoring Boolean functions to assist in educational logic designs. Our method for factorization is to implement two-cube Boolean division with supports of an expression. The number of literals in a factored form is a good estimate of the complexity of a logic function. Our empirical evaluation shows the improvements in literal counts over previous other factorization methods.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.12
• /
• pp.2181-2186
• /
• 2006

In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

• Journal of the Korea Computer Industry Society
• /
• v.7 no.4
• /
• pp.293-298
• /
• 2006

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Bryton's co-kernel cube matrix.

• The KIPS Transactions:PartA
• /
• v.15A no.1
• /
• pp.9-16
• /
• 2008

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.13 no.6
• /
• pp.20-23
• /
• 1976

A boolean algebra method for computing the reliability in a communication network is prosented. Given the set of all simple paths between two nodes in a network, the terminal reliability can be symbolically computed by the Boolean operation which is named parallel operation. The method seems to be promising for both oriented and nonoriented network.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.7
• /
• pp.1896-1907
• /
• 1998

확장된 마크흐름선도(EMFG: Extednded Mark Flow Graph)는 기존의 MFG를 개선한 그래프로서, 회로변수식에 의해 실제회로로 쉽게 구현가능하므로 이산제어시스템의 모델링과 설계 및 구현의 강력한 도구로 사용될 수 있다. 본 논문은 EMFG의 트랜지션들이 점화하는 과정 및 트랜지션들이 점화완료하였을 때 각 박스들의 마크수 변화를 부울함수식과 벡터를 사용하여 표현하였다. 또한 시스템의 상태변화를 쉽게 판단할 수 있게 하는 EMFG의 동작알고리듬을 제안하였으며, 제안된 알고리듬은 3-비트 증가계수기를 설계한 EMFG와 시간트랜지션이 포함된 가상의 EMFG에서 잘 수행되었다. EMFG의 동작이 부울함수로 해석가능해짐으로 인해 시스템의 분석 및 설계가 용이하며 컴퓨터를 이용한 자동화된 시스템의 분석과 설계가 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.7 no.1
• /
• pp.25-28
• /
• 1982

A method for finding the symbolic reliability expressision of a conbinational logic circuit is presented. The evaluation of the probabilities of the outputs can be symbolically evaluated by the Boolean operation named sharp operation, provided that every input of such a circuit can be treated as random variables with values set(0, 1) and the output of a circuit can be represented by a Boolean sum of produt expression.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.1
• /
• pp.25-34
• /
• 1981

Any logical stuckft faults in multivalued combinational circuits are analyzed using the concept of Boolean difference. The algebra employed is the implementation oriented algebra developed by Allen and Givone. All the lines in the circuit are classified into five types according to their properties. For each type, the equation that represents the complete test set is derived and proved. All the results in examples are confumed to be correct by comparing the truth tables of the normal and faulty circuits.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.5
• /
• pp.87-93
• /
• 2002

SHACAL is based on the hash standard SHA-1 used in encryption mode, as a submission to NESSIE. SHACAL uses the XOR, modular addition operation and the functions of bit-by-bit manner. These operations and functions make the differential cryptanalysis difficult, i.e, we hardly find a long differential with high probability. But, we can find short differentials with high probability. Using this fact, we discuss the security of SHACAL against the amplified boomerang attack. We find a 36-step boomerang-distinguisher and present attacks on reduced-round SHACAL with various key sizes. We can attack 39-step with 256-bit key, and 47-step with 512-bit key.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.7
• /
• pp.3251-3257
• /
• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts kernel-kernel pairs as well as cokernel-kernel pairs. The given logic expressions can be translated into Boolean divisors and quotients with kernel-kernel pairs. Next, kernel intersection method provides the common sub-expressions for several logic expressions. Experimental results show the improvement in literal count over previous other extraction methods.