• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.49-59
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• 2008

SIFT(Scale Invariant Feature Transform) is an algorithm to extract vectors at pixels around keypoints, in which the pixel colors are very different from neighbors, such as vortices and edges of an object. The SIFT algorithm is being actively researched for various image processing applications including 3-D image constructions, and its most computation-intensive stage is a keypoint localization. In this paper, we develope a fixed-point model of the keypoint localization and propose its efficient hardware architecture for embedded applications. The bit-length of key variables are determined based on two performance measures: localization accuracy and error rate. Comparing with the original algorithm (implemented in Matlab), the accuracy and error rate of the proposed fixed point model are 93.57% and 2.72% respectively. In addition, we found that most of missing keypoints appeared at the edges of an object which are not very important in the case of keypoints matching. We estimate that the hardware implementation will give processing speed of $10{\sim}15\;frame/sec$, while its fixed point implementation on Pentium Core2Duo (2.13 GHz) and ARM9 (400 MHz) takes 10 seconds and one hour each to process a frame.

• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.151-156
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• 2009

This paper proposes a Gaussian mixture model(GMM)-based music discrimination system for FM broadcasting. The objective of the system is automatically archiving music signals from audio broadcasting programs that are normally mixed with human voices, music songs, commercial musics, and other sounds. To improve the system performance, make it more robust and to accurately cut the starting/ending-point of the recording, we also added a post-processing module. Experimental results on various input signals of FM radio programs under PC environments show excellent performance of the proposed system. The fixed-point simulation shows the same results under 3MIPS computational power.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.265-268
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• 2006

데스크탑 환경의 멀티미디어 디스플레이 시스템은 고해상도, 대화면의 영상을 제공해 줄 수 있는 반면 제약된 공간에서만 동작하므로 휴대할 수 없는 문체가 있다. PDA, PMP와 모바일 폰과 같은 휴대성을 가지는 멀티미디어 디스플레이 시스템은 해상도가 낮아 사용자에게 충분한 몰입감을 제공 해 주지 못한다. 본 논문에서는 기존의 데스크탑 환경에서 동작하는 프로젝션 기반의 증강현실 시스템을 모바일 플랫폼으로 확장한 프로젝션 기반의 휴대형 멀티미디어 디스플레이 시스템을 제안한다. 제안된 시스템은 PDA와 포켓 프로젝터를 결합한 것으로, PDA에서 전 처리된 멀티미디어 영상을 포켓 프로젝터를 이용하여 임의의 모양을 가지는 스크린에 왜곡 없이 영상을 표시해 줄 수 있다. 개발환경은 Window Mobile 5.0 기반의 ARM 플랫폼을 사용하는 PDA를 이용하였고, 시스템의 최적화를 위하여 x86 플랫폼에 최적화된 OpenCV 라이브러리를 모바일용으로 변환하였다. 또한 모바일 플랫폼에서는 부동소수점 연산으로 인한 시스템의 속도저하 문제가 발생하기 때문에 부동소수점 연산을 정수 연산으로 변환함으로써 처리 속도를 개선하였다. 프로젝션 기반의 디스플레이 시스템을 실현하기 위해서 필요한 기술적인 과제들을 모바일 환경에서 직접 처리해 봄으로써 휴대형 프로젝션 기반의 멀티미디어 시스템의 가능성을 제시한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1593-1600
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• 2009

There are two major algorithms to find a square root of floating point number, one is the Newton_Raphson algorithm and GoldSchmidt algorithm which calculate it approximately by iterating multiplications and the other is SRT algorithm which calculates it exactly by iterating subtractions. This paper proposes an exact floating point square root algorithm using only multiplication. At first an approximate inverse square root is calculated by Newton_Raphson algorithm, and then an exact square root algorithm by reducing an error in it and a compensation algorithm of it are proposed. The proposed algorithm is verified to calculate all of numbers in a single precision floating point number and 1 billion random numbers in a double precision floating point number. The proposed algorithm requires only the multipliers without another hardware, so it can be widely used in an embedded system and mobile production which requires an efact square root of floating point number.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.102-112
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• 2007

This paper includes an analysis of face recognition algorithm to design hardware and presents fixed point model in accordance with it. Face recognition algorithm detects the positions of face and eyes to make use of their feature data to detect and verify human faces. It distinguishes a particular user by means of comparing them with registered face features. To implement the face recognition algorithm into hardware, we developed its fixed point model by analyzing face feature parameters, face acquisition data, and feature detection parameters and operation structure.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.305-306
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• 2007

This paper proposes an automatic conversion method from floating-point value computations to fixed-point value computations for implementing automatic speech recognition (ASR) algorithms in embedded device.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1153-1156
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• 1998

We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.380-389
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• 2005

The Goldschmidt iterative algorithm for a floating point divide calculates it by performing a fixed number of multiplications. In this paper, a variable latency Goldschmidt's divide algorithm is proposed, that performs multiplications a variable number of times until the error becomes smaller than a given value. To calculate a floating point divide '$\frac{N}{F}$', multifly '$T=\frac{1}{F}+e_t$' to the denominator and the nominator, then it becomes ’$\frac{TN}{TF}=\frac{N_0}{F_0}$'. And the algorithm repeats the following operations: ’$R_i=(2-e_r-F_i),\;N_{i+1}=N_i{\ast}R_i,\;F_{i+1}=F_i{\ast}R_i$, i$\in${0,1,...n-1}'. The bits to the right of p fractional bits in intermediate multiplication results are truncated, and this truncation error is less than ‘$e_r=2^{-p}$'. The value of p is 29 for the single precision floating point, and 59 for the double precision floating point. Let ’$F_i=1+e_i$', there is $F_{i+1}=1-e_{i+1},\;e_{i+1}',\;where\;e_{i+1}, If '$[F_i-1]<2^{\frac{-p+3}{2}}$ is true, ’$e_{i+1}<16e_r$' is less than the smallest number which is representable by floating point number. So, ‘$N_{i+1}$ is approximate to ‘$\frac{N}{F}$'. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal tables ($T=\frac{1}{F}+e_t$) with varying sizes. 1'he superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a divider. Also, it can be used to construct optimized approximate reciprocal tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia, scientific computing, etc