Design of Floating-point Processing Unit for Multi-chip Superscalar Microprocessor

다중 칩 수퍼스칼라 마이크로프로세서용 부동소수점 연산기의 설계

We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.