• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.24-36
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• 2003

The digital mobile communication will be developed till getting multimedia service in anyone, any where, any time. Theses requiring items are going to be come true via IMT-2000 system. Transmitting signal bandwidth of IMT-2000 system is 3 times as large as IS-95 system. That is mean peak to average of signal is higher than IS-95A system. So we have to design it carefully not to effect in adjacent channel. HPA(High Power Amplifier) located in the end point of system is operated in 1-㏈ compression point(Pl㏈), then it generates 3rd and 5th inter modulation signals. Theses signals affect at adjacent channel and RF signal is distorted by compressed signal which is operated near by Pl㏈ point. Then the most important design factor is how we make HPA having high linearity. Feedback, Pre-distorter and Feed-forward methods are presented to solve theses problems. Feed-forward of these methods is having excellent improving capacity, but composed with complex structure. Generally, Linearity and Efficiency in power amplifier operate in the contrary, then it is difficult for us to find optimal operating point. In this paper we applied algorithm which searches optimal point of linear characteristics, which is key in Power Amplifier, using minimum current point of error amplifier in 1st loop. And we made 2nd loop compose with new structure. We confirmed fabricated LPA is operated by having high linearity and minimum current condition with ACPR of -26 ㏈m max. @ 30㎑ BW in 3.515㎒ and ACLR of 48 ㏈c max@${\pm}$㎒ from 1W to 40W.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1650_1651
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• 2009

DC/DC 승압 컨버터는 인덕터 내부 저항으로 인하여 부하 저항의 변화가 시스템 동작점에 영향을 미치게 되며, 이로 하여 제어기 설계의 기준이 되는 선형화된 모델은 불확실성을 가지게 된다. 본 논문은 인덕터의 내부 저항과 출력단의 부하 변동으로 인한 불확실성에 대하여 출력 전압의 강인성을 향상시키기 위해 PI 관측기 기반 적분형 상태 변수 궤환 제어기를 제안한다. PI 관측기는 불확실한 시스템 제어에 널리 사용되는 오차의 적분항을 Luenberger 관측기에 추가한 형태로써 불확실성에 강인한 추정 성능을 보인다. 모의실험을 통해 불확실성이 존재하는 경우 제안된 제어기의 강인성을 확인하고 설계된 관측기가 Luenberger 관측기에 비해 상태변수 추정 성능이 우수함을 보인다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.154-156
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.439-440
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• 2017

본 논문에서는 지능형 반도체 변압기를 구성하는 Dual Active Bridge (DAB) 컨버터와 계통 연계형 인버터와의 연결에 따른 임피던스 영향을 분석하기 위해 컨버터의 입력 임피던스와 인버터의 출력 임피던스 각각에 대한 전달함수를 분석하고자 한다. 이를 통해 인버터와 컨버터 간의 임피던스 영향을 이론 분석과 모의 시험을 통해 확인하고, 제어기의 설계 방향을 제안하고자 한다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1104-1112
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• 2013

This paper presents a wideband Colpitts voltage controlled oscillator(VCO) with nanosecond startup time and a center frequency of 8.35 GHz for a new bubble-type motion detector that has a bubble-layer detection zone at the specific distance from itself. The VCO circuit consists of two parts; one is a negative resistance part with a HEMT device and Colpitts feedback structure and the other is a resonator part with a varactor diode and shorted shunt microstrip line. The shorted shunt microstrip line and series capacitor are utilized to compensate for the input reactance of the packaged HEMT that changes from capacitive values to inductive values at 8.1 GHz due to parasitic package inductance. By tuning the feedback capacitors which determine negative resistance values, this paper also investigates startup time improvement with the negative resistance variation and tuning bandwidth improvement with the reactance slope variation of the negative resistance part. The VCO measurement shows the tuning bandwidth of 2.3 GHz(28 %), the output power of 4.1~7.5 dBm and the startup time of less than 2 nsec.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.167-172
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• 2006

In this paper, the 25W power amplifier for UHF band radio transceiver has been designed and realized. The power amplifier was composed of drive, power amplifier and control stages. Feedback topology and coaxial line baluns were used for wide band operation. The VDMOS, which has reliable performance for linearity and efficiency, was used for power device and designed to operate as push-pull amplification at Class AB Bias. The power amplifier designed in such a way was found to show stable AM modulation performance when voice signal was detected at the gate stage, with being designed and realized to meet output specifications of commercial air traffic control transmitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.3
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• pp.214-221
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• 1998

A new control approach using neural network for the robust position control of a BRUSHLESS direct drive(BLDD) motor is presented. The linear quadratic controller plus feedforward neural network is employed to obtain the robust BLDD motor system approximately linearized using field-orientation method for an AC servo. The neural network is trained in on-line phases and this neural network is composed by a feedforward recall and error back-propagation training. Since the total number of nodes are only eight, this system will be easily realized by the general microprocessor. During the normal operation, the input-output response is sampled and the weighting value is trained by error back-propagation at each sample period to accommodate the possible variations in the parameters or load torque. And the state space analysis is performed to obtain the state feedback gains systematically. In addition, the robustness is also obtained without affecting overall system response.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.371-383
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• 2004

In this paper we consider technological requirements to broadcast digital television signals using single frequency networks (SFN) in the Advanced Television Systems Committee (ATSC) transmission systems and propose equalization digital on-channel repeater (EDOCR) that overcomes the limitations of conventional digital on-channel repeaters (DOCRs). Since there are no forward error correction (FEC) decoder and encoder, the EDOCR does not have an ambiguity problem. In addition, since an adaptive equalizer in the EDOCR removes multi-path signals, additive white Gaussian noise (A WGN), and feedback signal due to low antenna isolation, the EDOCR may have good output signal quality with high power.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.