• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.5
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• pp.504-511
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• 2016

In this paper, MIMO system based on turbo equalization techniques which LDPC codes were outer code and space time trellis codes (STTC) were employed as an inner code are studied. LDPC decoder and STTC decoder are connected through the interleaving and de-interleaving that updates each other's information repeatedly. In conventional turbo equalization of MIMO system, BCJR decoder which decodes STTC coded bits required two-bit wise decoding processing. Therefore duo-binary turbo codes are optimal for MIMO system combined with STTC codes. However a LDPC decoder requires bit unit processing, because LDPC codes can't be applied to these system. Therefore this paper proposed turbo equalization for MIMO system based on LDPC codes combined with STTC codes. By the simulation results, we confirmed performance of proposed turbo equalization model was improved about 0.6dB than that of conventional LDPC codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1468-1476
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• 1997

In mobile communication systems, the Reduced State Sequence Estimation(RSSE) receiver must be able to track changes in the channel. This is carried out by the adaptive channel estimator. However, when the tentative decisions are used in the channel estimator, incorrect decisions can cause error propagation. This paper presents a new channel estimator using the path history in the Viterbi decoder for preventing error propagation. The selection of the path history in the Viterbi decoder for preventing error propagation. The selection of the path history for the channel estimator depends on the path metric as in the decoding of the Viterbi decoder in RSSE. And a discussion on the channel estimator with different adaptation algorithms such as Least Mean Square(LMS) algorithm and Recursive Least Square(RLS) algorithm is provided. Results from computer simulations show that the RSSE receivers using the proposed channel estimator have better performance than the other conventional RSSE receiver, and that the channel estimator with RLS algorithm is adequate for multipath fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.28-31
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• 2010

분산 비디오 부호화 시스템(distributed video coding:DVC)에서는 기존의 비디오 부호화 시스템과는 달리 부호기가 아닌 복호기에서 움직임 추정 연산을 함으로써 부호기의 복잡성을 크게 줄일 수 있다. DVC 시스템의 복호기에서 생성되는 부가정보(side information : SI)는 전체 DVC 시스템의 성능에 큰 영향을 미친다. DVC 시스템의 복호기에서 SI 정보를 생생하기 위해서 움직임 보상 보간(motion compensated interpolation : MCI) 기법이 많이 사용되는데 본 논문에서는 다양한 MCI 기법들의 성능을 분석한다.

• Journal of Internet Computing and Services
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• v.10 no.1
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• pp.1-9
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• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• Electronics and Telecommunications Trends
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• v.15 no.4 s.64
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• pp.12-22
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• 2000

1993년 Shannon 한계에 근접하는 우수한 성능을 가진 터보 부호가 발표된 이후 그에 대한 많은 연구들이 이루어져 왔지만, 한편으로는 반복 복호의 복잡도와 이로 인한 복호 지연을 고려할 때 실제 시스템에 적용이 가능할 것인가에 대한 의문 역시 함께 제기되어 왔다. 그러나 터보 부호를 구현하고자 하는 노력은 계속되었으며, 현재는 터보 부.복호기를 구현한 제품들이 시장에 등장한 상태이다. 특히 위성통신시스템에서의 적용을 위한 노력이 증가하고 있으며 곧 그 구현을 앞두고 있는 IMT-2000 시스템에서도 터보 부호는 일부 서비스에서 활용될 예정 등으로 앞으로 그 활용도는 급격히 늘어날 전망이다. 터보 부.복호기를 한 칩에 구현한 제품들도 이미 출시되어 있는 상태이다. 터보 부.복호기를 하드웨어로 구현한 제품들은 크게 길쌈 터보 부호를 사용한 것과 블록 터보 부호를 사용한 것으로 양분된다. 본 논문에서는 실제 상용 하드웨어로 구현되어 있는 터보 부호의 특징과 성능을 분석한 내용을 기술하고자 한다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.3
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• pp.164-168
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies Horizontal Shuffle Scheduling (HSS) algorithm. In the result, number of iteration is half than conventional algorithm without performance degradation. Finally, this paper present design methodology of high-speed LDPC decoder and confirmed its throughput is up to about 600Mbps.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1627-1630
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• 2002

본 논문은 역추적 예견 알고리즘을 사용한 비터비 복호기에서의 TB단의 Polling 구조의 단순화 방법을 제시한다. 비터비 복호기의 3대 Unit중 하나인 Trace Back에서 역추적 예견 알고리즘을 사용할 경우 복호화 시점에서의 최소 State Metric 값을 찾아야 하는 번거로움을 줄일 수 있다. 하지만 복호 신호의 신뢰도 분산에 따라 Polling Unit 이 추가되어야 함에 따라 실제 하드웨어 복잡도에서의 이득은 미미한 것으로 알려져 있다. 제시된 구조에서는 Polling Unit을 단순화 할 수 있는 방법을 적용하였다. 기존 하드웨어와의 비교 평가를 위하여 IEEE802.11a의 표준에 따른 부호화율 1/2, 구속장 7을 갖는 비터비 디코더에 대하여 역추적 예견 알고리즘과 파이프라인 구조만을 갖는 경우와 제안된 단순화한 Polling Unit을 적용한 구조와의 비교에서 Trace Back Unit에서 약 45%의 감소 효과를 보였다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.