• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.1
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• pp.53-60
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• 1996

오증 요소로부터 오류위치다항식의 계수를 계산함으로서 (23,12) Golay 부호를 복호할 수 있는 대수적 복호법이 최근 증명되었다. GF(2)상에서의 3중 오류정정 BCH부호의 복호법을 이 부호에 완벽하게 적용하여 해석하는 것을 소개한다. 그리고 GF(2)에 대한 최적의 정규기저를 구하여 이를 유한체 연산에 적용하며 단계별로 복호 회로의 구성을 제시한다. 이는 기존의 복호기보다 논리회로적으로 간단하며, 복호된 정보를 얻기까지 35번의 치환이 필요하다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.93-106
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• 1998

RS부호의 복호 기법은 전체 통신 시스템의 성능 및 복잡도에 큰 영향을 미친다. 지금까지 RS부호의 복호 기법은 다양한 방법에 있으나Euclid알고리즘과 변환복호기법을 이용한 복호 기법은 오류정정능력이 큰 복호 기법으로 널리 적용되고 있다. 본 논문에서는 오류정정능력이 5이상인 RS부호의 복호 알고리즘에 적용될 수 있는 효율적인 복호 알고리즘을 제시하고, 이를 이용하여 5중 오류 정정(31, 21)RS 부호기 및 복호기를 설계하고VHDL을 사용한 컴퓨터 시뮬레션을 통해서 그 타당성을 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.546-552
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• 2000

The decoding of Turbo-Code relies on the application of a soft input/soft output decoders which can be realized using maximum-a-posteriori(MAP) symbol estimator[l]. Radix-2 MAP decoder can not be used for high speed communications because of a large number of interleaver block size N. This paper proposed a new simple method for radix-4 MAP decoder based on radix-2 MAP decoder in order to reduce the interleave block size. A branch metrics, forward and backward recursive functions are proposed for applying to radix-4 MAP structure with symbol interleaver. Radix-4 MAP decoder shall be illustratively described and its error performance capability shall be compared to conventional radix-2 MAP decoder in AWGN channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.75-82
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• 2006

In this paper, a space-frequency coded orthogonal frequency division multiplexing (SFC-OFDM) scheme with dual Viterbi decoder is proposed and analyzed. Here, two independent half-rate OFDM symbols are generated after convolutional coding of the binary source code. A dual Viterbi decoder is exploited to decode the demodulated sequences independently in the receiver, and their path metrics are compared. Accordingly, the recovered binary data in the proposed scheme are composed of the combination of the sequences having larger path metrics while those in a conventional system are simply the output of single Viterbi decoder. As a result, the proposed SFC-OFDM scheme has a better performance than the conventional one for all signal-to-noise power ratio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.592-598
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• 2001

IMT-2000에서는 이미 터보코드가 채널코딩 기법으로 제안되어 있으며 특별히 3GPP 규격에서는 제한길이 4인 1/3 터보코드가 채택되어 있다. 기존의 논문에서는 일반적인 터보 코드의 성능에 대한 분석이 많이 제시되어 왔으나, 3GPP 규격의 터보 복호를 위한 SOVA 복호기의 성능 파라미터 추출과 그에 따른 성능 분석 수행되지 않았다. 본 연구에서는 효율적인 구조의 3GPP SOVA 복호기를 설계하기 위해서 외부정보의 스케일링과 신뢰도 갱신길이 라는 두 가지 파라미터에 따른 SOVA 복호기의 성능을 분석하고 최적의 파라미터 값을 제시하고자 한다. 이 파라미터의 최적화를 위하여 C++를 이용한 모의실험 결과, 3GPP 규격의 (13,15) 1/3 코드에서 스케일링 값은 1/2로 신뢰도 갱신길이는 10으로 최적화 되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.53-64
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• 2011

In this paper, we propose a channel estimation of side information method based received motion vectors for distributed video coding. The proposed decoder estimates motion vectors of side information and transmits it to the encoder. As the proposed encoder generates side information which is the same to one in the decoder with received motion vectors, accuracy of side information of the decoder is assessed and it is transmitted to decoder. The proposed decoder can also estimate accurate crossover probability with received error information. As the proposed method conducts correct belief propagation, computational complexity of the channel decoder decreases and error correction capability is significantly improved with the smaller amount of parity bits. Experimental results show that the proposed algorithm is better in rate-distortion performance and it is faster than several conventional distributed video coding methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.41-51
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• 2001

In this paper, we presented that the performance of the TCM(Trellis Coded Modulation) using the Euclidean distance is better than that of the convolutional code using the hamming distance under the same bandwidth efficiency. And the TCM DECODER for next generation mobile communication replacing the using convolutional decoder is implemented. Also, for the implementation of the TCM DECODER, the convolutional decoder and the TCM decoder were made by C-language and simulated under AWGN channel with respect to the hard decision and the soft decision. So we proved that performance of the TCM is better than that of the convolutional code. From this result, TCM DECODER, of which constraint length is 3, 5 or 7 and which use the soft decision method, was implemented using the AHDL(Altera Hardware Description Language) and fortified using the Max+plus H version 8.2 of Altera corporation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.