• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.307-310
• /
• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.35-41
• /
• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.4
• /
• pp.157-164
• /
• 2009

An efficient pipeline MDC Radix-4 FFT structure is proposed in this paper. Every stages in pipeline FFT structure consists of delay' commutator and butterfly. Proposed butterflies in front and rear stages utilize CORDIC and Common Sub-expression Sharing(CSS) techniques, respectively. It is shown that proposed butterfly structure can reduce the number of adders through sharing common patterns of CSD type coefficients. The Verilog-HDL modeling and Synopsys logic synthesis results that the proposed structure show 48.2% cell area reduction in the complex multiplication part and 22.1% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structures. Consequently, the proposed FFT structure can be efficiently used in various OFDM systems.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.20 no.6
• /
• pp.69-74
• /
• 1983

This paper discussed the high speed complex multiplier based on the Residue Number System (RNS) using combinational logic circuits. In addition, the sigil determination and overflow correction problem in residue addition has been studied. The estimated multiplication time of considered processor were about 53.15 ns.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.37 no.1
• /
• pp.1-11
• /
• 2000

We propose a predistorter to compensate for nolinear distortion induced by a high power amplifier employed in multi carrier-code division multiple access (MC-CDMA) systems. The proposed scheme rests upon the fixed point iteration (FPI) associated with the contraction mapping theorem. Unlike the predistorter based on the FPI already presented by the authors in other literatures which operates on complex-valued modulation signals, the proposed predistorter in this paper deals with real-valued FPI on modulation signal amplitudes, resulting in less complexity. Simulation results on a BPSK-modulated, 64-subcarrier synchronous MC-CDMA baseband system with a traveling wave tube amplifier in the transmitter, indicate that the proposed predistorter achieves significant improvement in terms of bit error rate and total degradation over those without the predistorter. Moreover, the proposed predistorter outperforms the complex-valued counterpart, in particular, for small output back-off levels.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.2015-2024
• /
• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of Educational Research in Mathematics
• /
• v.25 no.2
• /
• pp.177-188
• /
• 2015

In this paper, I investigated the historical development process for the product of two vectors in the plane and space, and draw implications for educational guidance to internal and external product of vectors based on it. The results of the historical analysis show that efforts to define the product of the two line segments having different direction in the plane justified the rules of complex algebraic calculations with its length of the product of their lengths and its direction of the sum of their directions. Also, the efforts to define the product of the two line segments having different direction in three dimensional space led to the introduction of quaternion. In addition, It is founded that the inner product and outer product of vectors was derived from the real part and vector part of multiplication of two quaternions. Based on these results, I claimed that we should review the current deployment method of making inner product and outer product as multiplications that are not related to each other, and suggested one approach for connecting the inner and outer product.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.40 no.6
• /
• pp.127-140
• /
• 2003

This paper develops a novel algorithm of computing 2 Dimensional Discrete Cosine Transform (2D-DCT) via Polynomial Transform (PT) converting 2D-DCT to the sum of 1D-DCTs. In computing N${\times}$M size 2D-DCT, the conventional row-column algorithm needs 3/2NMlog$_2$(NM)-2NM＋N＋M additions and 1/2NMlog$_2$(NM) additions and 1/2NMlog$_2$(NM) multiplications, while the proposed algorithm needs 3/2NMlog$_2$M＋NMlog$_2$N-M-N/2＋2 additions and 1/2NMlog$_2$M multiplications The previous polynomial transform needs complex operations because it applies the Euler equation to DCT. Since the suggested algorithm exploits the modular regularity embedded in DCT and directly decomposes 2D DCT into the sum of ID DCTs, the suggested algorithm does not require any complex operations.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.13 no.5
• /
• pp.917-922
• /
• 2018

In the conventional interchannel interference self-cancellation (ICI-SC) schemes, the length of sampling window is the same as the symbol length of orthogonal frequency division multiplexing (OFDM). Thus, the number of complex operations to compute the interference coefficient of each subchannel is significantly increased. To solve this problem, we present an approximated mathematical model for the coefficients of ICI-SC schemes. Based on the proposed approximation, we analyze mean squared error (MSE) and computational complexity of the ICI-SC schemes with the length of sampling window. As a result, the presented approximation has an error of less than 0.01% on the MSE compared to the original equation. When the number of subchannels is 1024, the number of complex computations for the interference coefficients is reduced by 98% or more. Since the computational complexity can be remarkably reduced without sacrificing the self-cancellation capability, it is considered that the proposed approximation is very useful to develop an algorithm for the ICI-SC scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.53-60
• /
• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.