• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.549-560
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• 2001

Cluster system provides attractive scalability in terms of compution power and memory size. With the advances in high speed computer network technology, cluster systems are becoming increasingly competitive compared to expensive MPPs (massively parallel processors). Load balancing is very important issue since an inappropriate scheduling of tasks cannot exploit the true potential of the system and can offset the gain from parallelization. In parallel processing program, it is difficult to predict the load of each task before running the program. Furthermore, tasks are interdependent each other in many ways. The dynamic load balancing algorithm, which evaluates each processor's load in runtime, partitions each task into the appropriate granularity and assigns them to processors in proportion to their performance in cluster systems. However, if the communication cost between processing nodes is expensive, it is not efficient for all nodes to attend load balancing process. In this paper, we restrict a processor that attend load balancing by the communication cost and the deviation of its load from the average. We simulate various models of the cluster system with parameters such as communication cost, node number, and range of workload value to compare existing load balancing methods with the proposed dynamic algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of Advanced Navigation Technology
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• v.25 no.3
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• pp.229-235
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• 2021

This paper proposes a method of implementing an unequal power divider for high splitting ratios by using transmission lines connected with open and short stubs. The proposed method is an equivalent circuit analysis of a transmission line with an additional port so that it can be converted to an arbitrary impedance in the center of a 2-port transmission line and a 3-port transmission line with an open or short stub connected in parallel to each port. To prove the validity of this method, a Wilkinson power divider with k² = 20 dB splitting ratio and a Gysel power divider with k² = 17 dB splitting ratio were designed at a center frequency of 1 GHz using a 3-port transmission line equivalent circuit. The experimental results of the electrical characteristics are in good agreement with the simulation.

• Journal of Convergence for Information Technology
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• v.11 no.2
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• pp.41-46
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• 2021

The method of the edge detection algorithm based on grayscale mathematical morphology has the advantage that image noise can be removed and processed in parallel, and the operation speed is fast. However, the method of detecting the edge of an image using a single structural scale element may be affected by image information. The characteristics of grayscale morphology may be limited to the edge information result of the operation result by repeatedly performing expansion, erosion, opening, and containment operations by repeating structural elements. In this paper, we propose an edge detection algorithm that applies a structural element with strong directionality to noise and then applies weighted entropy to each pixel information in the element. The result of applying the multi-scale structural element applied to the image and the result of applying the directional weighted entropy were compared and analyzed, and the simulation result showed that the proposed algorithm is superior in edge detection.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.71-76
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• 2022

Since brightness is proportional to the operating current, a method of connecting several LEDs in series and driving with a constant current source is widely used for driving circuits of LED lights. Because several LEDs are connected in series, if some LEDs open due to a fault, the current path is broken and all other LEDs connected in series are turned off. In this paper, we designed a circuit to solve this problem by connecting a Zener diode having a breakdown voltage of about 0.4V higher than the LED operating voltage in parallel with each LED to create a current bypass in case of LED failure. Through simulations and experiments, it was confirmed that the current of the Zener diode hardly flows when the LED is operating normally, and that the Zener diode stably operates as a current bypass when the LED fails.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.2
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• pp.71-76
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• 2022

Round-robin is widely used for the scheduling of large-scale parallel workloads in the computing units of GPGPU. Round-robin is easy to implement by sequentially allocating tasks to each computing unit, but the load balance between computing units is not well achieved in multi-workload environments like cloud. In this paper, we propose a new thread block scheduling policy to resolve this situation. The proposed policy manages thread blocks generated by various GPGPU workloads with multiple queues based on their computation loads and tries to maximize the resource utilization of each computing unit by selecting a thread block from the queue that can maximally utilize the remaining resources, thereby inducing load balance between computing units. Through simulation experiments under various load environments, we show that the proposed policy improves the GPGPU performance by 24.8% on average compared to Round-robin.

• Journal of IKEEE
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• v.25 no.4
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• pp.741-749
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• 2021

This paper presents the current-fed type LLC AC to DC high frequency resonant converter capable of ZVZCS(Zero-Voltage and Zero-Current Switching). The current-fed type LLC AC to DC high frequency resonant converter proposed in this paper could operate not only in ZVS(Zero-Voltage Switching) operation by connecting the resonant capacitors(C₁, C₂) in parallel across the switching devices but also in ZCS(Zero-Current Switching) operation of the secondary diode. The ZVS and ZCS operations can reduce the turn-on loss of the switching devices and the turn-off loss of the secondary diodes, respectively. The circuit analysis of current-fed type LLC AC to DC high frequency resonant converter proposed in this paper is addressed generally by adopting the normalized parameters. The operating characteristics of proposed LLC AC to DC high frequency resonant converter were also evaluated by using the normalized control parameters such as the normalized control frequency(μ), the normalized load resistor(λ) and so on. Based on the characteristic values through the characteristics of evaluation, an example of the design method of proposed LLC AC to DC high frequency resonant converter is suggested, and the validity of the theoretical analysis is confirmed using the experimental results and PSIM simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.178-180
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• 2020

기존의 철도차량용 무선전력전송 시스템은 Medium-voltage (MV) 60 Hz 중전압 AC 계통 전압을 Low-voltage (LV) DC로 변환하기 위해 저주파 변압기와 정류기를 사용한다. 하지만 수 MW급의 대전력을 낮은 DC 전압으로 전송하려면 인버터는 수백 A - 수 천 A 이상의 전류용량을 가져야하므로 정류기의 출력 단에 직렬 또는 병렬로 연결된 여러 개의 고주파 변압기를 필요하게 된다 (그림 1참조). 이러한 저주파 변압기, 정류기 및 고주파 변압기는 크고 무거우므로 낮은 전력밀도 및 높은 시스템 가격의 원인이 된다. 본 논문에서는 이러한 저주파변압기, 정류기, 고주파 변압기를 사용하지 않는, 여자 코일을 이용한 새로운 멀티레벨 무선전력전송 시스템의 토폴로지를 제안한다. 제안된 멀티레벨 무선전력전송 시스템은 멀티레벨 인버터의 각 출력 단에 여자코일 (excitation coil) 이 연결되어 있다. 이 여자코일들은 급전코일 (transmitter coil) 에 전기적으로는 절연되었지만 자기적으로 강하게 결합된다. 여자코일들이 발생시킨 자기장은 급전코일에 유도전압을 발생시키고, 급전코일에서 수백 A 이상의 큰 전류를 흐르게 하여 급전코일에서 강한 자기장을 발생하도록 한다. 이 자기장은 급전코일과 수 cm 이상 떨어져 자기적으로 약하게 결합된 집전코일 (receiver coil) 에 다시 유도전압을 발생시켜 전력을 전달하게 된다. 제안한 새로운 멀티레벨 무선 전력 전송 시스템은 시뮬레이션을 통해 검증했다.

• Journal of IKEEE
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• v.16 no.3
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• pp.217-223
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• 2012

This paper presents design and operational characteristics of 150 MW pulse power system for high current pulse forming network to control trigger time. The system is composed of two capacitor bank modules. Each capacitor bank module consist of a trigger vacuum switch, 9k 33kJ capacitor, an energy dump circuit, a crowbar circuit and a pulse shaping inductor and is connected in parallel. It is controlled by trigger controller to select operational module and determine triggering time. Pspice simulation was conducted about determining parameters of components such as crowbar circuit, capacitor, pulse forming inductor, trigger vacuum switch and predicting results of experiment circuit. The result of the experiment was in good agreement with the result of the simulation. The various current shapes with 300~650 us pulse width is formed by sequential firing time control of capacitor bank module. The maximum current is about 40 kA during simultaneous triggering of two capacitor bank modules. The developed 150 MW pulse power system can be applied to high current pulse power system such as rock fragmentation power sources, Rail gun, Coil gun, nano-powers, high power microwave.