• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.6
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• pp.504-511
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• 2003

In this paper, inverter type neon power supply using a piezoelectric transformer is fabricated and its characteristic is investigated. Developed neon power supply is composed of basic circuit and blocks, such as rectifier part, frequency oscillation part and piezoelectric transformer and resonant half bridge inverters. In this paper for complement the low power limitation, piezoelectric transformer at parallel connected driving by inverter is studied for noon tubes system of high power. When piezoelectric transformer is connected with parallel, LC filter connection method with parallel and selection of inductance L and capacitor C of primary side is suggested for reduce unbalanced current at the terminal of each transformer. Piezoelectric transformers use piezoelectric ceramic devices. Thus it is wireless therefore it has high power density, high Isolation level, low loss, more light, and miniaturization. In addition, high voltage transfer ratio is expected because there is no leakage inductance. Also, it has economic merit that the electrical loss Is low because structure is simple, small and tighter weight.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.2
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• pp.1-5
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• 2017

In this paper, we propose a wideband band-stop filter (BSF) in order to extend the stopband of the band-stop filter using a symmetric dual spurline and the coupled open stub. First, we know that the symmetric dual spurline structure is advantageous in widening the stopband, as compared to the asymmetric dual spurline structure. So we designed a band-stop filter that combines the electrically coupled open stub (ECOS) band-stop filter with a symmetric dual spurline. We can greatly extend the stopband, when it is combined with the dual spurline and electrically coupled open stub on a microstrip transmission line, without any size increment. The stopband of the proposed band-stop filter is extended by approximately 244% (rejection depth: -20 dB) compared with a band-stop filter without a dual spurline.

• Journal of Korean Society of Water and Wastewater
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• v.16 no.6
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• pp.670-678
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• 2002

Since Korean government imposed a stricter regulation on effluent T-N and T-P concentrations from wastewater treatment plant, a new process has to be developed to meet these rules and this process should remove T-N and T-P, economically, from weak wastewater that is typical for Korea's combined sewer system sewage. In this study, a computer simulator, BioWin from EnviroSim, Inc. was used. Three processes - A2/O, Modified Johannesburg, UCT- had been simulated under same operational conditions and a new process - Parallel BNR Process - had been developed based on these simulation results. The Parallel BNR process consists of two rows of reactors: One row has anaerobic and aerobic reactors in series, and the other row has RAS anoxic1 and RAS anoxic2 reactors in series. In order to ensure anaerobic state in anaerobic tank, a part of influent is fed to RAS anoxic1 tank in second row. This process had been simulated under same conditions of other three processes and the simulation results were compared. The results showed that three existing processes could not perform biological phosphorus removal when the average influent was fed at any operation temperatures. However, the Parallel BNR process was found that biological phosphorus removal could be performed when both design and average influent were fed at any operation temperatures. This process showed the T-N concentration in effluent had a maximum value of 15mg/L when design influent was fed at $13^{\circ}C$ and a minimum value of 14mg/L when average influent was fed at $20^{\circ}C$. Also, T-P concentrations had a maximum value of 1.3mg/L when average influent was fed at $20^{\circ}C$ and a minimum value of 1.1mg/L when design influent was fed at $13^{\circ}C$. Based on these results, we found that this process can remove nitrogen and phosphorus biologically under any operational conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.4 s.316
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• pp.55-60
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• 2007

In high field (> 3 T) MR imaging, the magnetic field inhomogeneity in the target object increases due to the nonuniform electro-magnetic characteristics of the relatively high RF frequency. Especially in the body imaging, the effect causes more serious problems resulting in locally high SAR(Specific Absorption Ratio). In this paper, we propose an optimized parallel-transmission RF coil and show the utility of the coil by FDTD simulations to overcome the unwanted effects. Three types of TX coil elements are tested to maximize the efficiency and their driving patterns(amplitude and phase) optimized to have adequate field homogeneity, proper SAR level, and sufficient field strength. For the proposed coil element of $25cm{\times}8cm$ loop structure with 12 channels for a 3.0 T body coil, the field non-uniformity of more than 70% without optimization was reduced to about 26 % after the optimization of driving patterns. The experimental as well as simulation results show that the proposed parallel driving scheme is clinically useful for (ultra) high field MRI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of Biomedical Engineering Research
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• v.20 no.4
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• pp.479-484
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• 1999

본 연구에서는 사람의 턱 운동과 턱 사이에 작용하는 힘(혹은 압력)을 그대로 나타낼 수 있는 저작로봇을 개발하는 것을 궁극적인 목표로 한다. 이러한 저작로봇이 개발되면, 치과의사가 환자의 턱운동에 나타나는 병변을 진단하고 치료하는데 큰 도움이 될 것으로 사료된다. 또한 , 본 연구에 채택한 병렬기구(parallel mechanism)에대한 순기구학적( forward kinematics)분석은 일반적인 병렬기구의 실계에도 응용될 것으로 기대된다. 본 연구진이 1차적으로 설계한 모델은 베이스와 플랫폼(platform), 그리고 이 둘을 연결하는 3개의 다리로 구성되어 있다. 다리와 플랫폼은 3자유도의 관절로 다리와 베이스는 1자유도의 경첩 관절로 연결되어 있으며, 이 3개의 경첩 관절은 베이스 위의 수평면에서 직선을 따라 움직인다. 경첩 관절의 수평 변위와 세 다리의 길이가 주어졌을 때 플랫폼의 위치와 오리엔테이션을 구하는 순기구학의 해( 解)를 계산해내는 알고리즘을 개발하였다. 이 알고리즘의 특징은 매 순간 오차를 계산하여 이 오차가 줄어드는 방향으로 나아가도록 시간간격(time step)을 조절하는 것이다. 본 알고리즘은 현재 가장 보편적으로 사용되고 있는 뉴튼-렙슨 방법에 비하여 3가지 장점을 나타내고 있다. 우선 , 초기치(initial guess)에 관계없이 수렴한다는 것이다. 또한, 본 알고리즘은 뉴튼-렙슨 방법에 비하여 수렴속도가 훨씬 빠르며, 연산 시간이 매우 짧아져 실제적인 실시간 적용에 적합하다. 마지막으로, 뉴튼-렙슨 방법에서는 여러 개의 해 가운데 어느 곳으로 수렴할 지 예측 할수 없으나 본 알고리즘에서는 초기치에 가장 가까운 해로 수렴한다. 이러한 순기구학의 다중성(multiplicity)문제를 해결하기 위하여 두 개의 조건을 제시하였으며, 이를 적용한 시뮬레이션 결과에 의하면 항상 원하는 해(true solution)에 수렴할 수 있었다.발생량의 감소를 기대 할 수 있는 친환경기술로 유지관리비를 최소화할 수 있는 장점이 있었다. 않은 사람들 중 미래의 검진실행의지에 건강소식지가 영향을 미친 경우는 48.7%였다. 보건교육을 받은 후 유방암 자가검진 실천율은 사업군에서 53.9%로 받기 전의 27.3%보다 증가하였으나 대조군의 경우는 별 차이가 없었다. 연령별로는 60대가 가장 높았고 사업군에서 검진율의 증가분은 30대가 가장 컸다. 교육수준별로는 사업군은 고졸이, 대조군은 전문대졸이 가장 높았고 사업군에서 검진율의 증가분은 고졸에서 가장 컸다. 보건교육 후 유방암과 관련된 건강지식의 정도는 사업군이 3.7점으로 대조군보다 유의하게 높았으며, 유방암 자가검진법을 실천하는 사람들의 동기는 ‘일반 대중매체의 영향’이 가장 많았으며 건강소식지가 동기인 경우도 20.4%였다. 사업군에서 건강소식지가 유방암 자가검진법 실천에 영향을 미친 경우가 79.6%였으며 유방암 자가검진법에 관한 보건교육을 받고 실천하지 않은 사람들 중 미래의 실천의지에 건강소식지가 영향을 미친 경우는 43.6%였다. 이상의 소견에서 지역주민을 대상으로 인쇄매체를 통한 보건교육은 인쇄물만으로도 쉽게 실천 할 수 있는 유방암 자가검진법이 가장 효과적이었으며, 자궁암검진에 관해서도 검진을 받을 수 있도록 지역사회의 보건의료의 하부구조를 정비하여 제도적 장치를 마련하고 정보를 제공한다면 자궁암검진 실천율도 증가할 것이다.고 12.9% 의 발달율을 보여 유의적인 차이를 보이지 않았다. 이상의 결과로 보아 핵이식 수정란을 효율적으로 생산하기 위하여 수핵난자의 세포질에 ionomycin 과 DMAP 의 혼합처리로 탈핵난자의 활성화를 유도하는 것이 효율을 증진시킬 수 있었다고 본다. 또한 공핵수정란을 수정 후 90시간과 114시간 개별 배양하여 할구를 공핵체로 핵이식에 이용하였을 때도 그룹배양에 비하여 효율이 떨어지지 않음을 알 수 있었으며, 수정란의 할구

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.61-71
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• 2007

The instruction level parallelism, which has been used to improve the performance of processors, expose its limit. The change of a control flow by a branch miss prediction is one of the obstacles that restrict the instruction level parallelism. The single chip multiprocessors have been developed to utilize the thread level parallelism. However, we could not use the maximum performance of the single chip multiprocessor in case of executing the coded programs without considering the multi-thread. In order to overcome the two performance degradation factors, in this paper, we suggest the concurrent branch execution method that applies to the multi-path execution method at a single chip multiprocessor. We executes all two flows of the conditional branch using the idle core processor. Through this, we can improve the processor's efficiency with blocking the control flow termination by the branch instruction and reducing the idle time. We analyze the effects of concurrent branch execution proposed in this paper through the simulation. As a result of that, concurrent branch execution reduces about 20% of idle time and improves the maximum 10% of the branch prediction accuracy. We show that our scheme improves the overall performance of maximum 39% compared to the normal single chip multiprocessor and maximum 27% compared to the superscalar processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.80-85
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• 2011

The mount of network traffic from the Internet is increasing because of the use of Broadband Convergence Networks(BcN). Network traffic is also increasing because of the development of application, especially multimedia traffic from IPTV, VOD, and online games. This multimedia traffic not only has a huge payload but also should be considered a threat in real time. For this reason, this study examines the ways that routers distribute the bandwidth in accordance to traffic properties. To classify the property of the traffic, it is essential to analyze the application layer. However, the general network processor architecture serially processes the L2-4 and L7 layer. We propose a novel parallel network processor architecture with a global cache that processes L2-4 and L7 in parallel. To verify the proposed architecture, we simulated both of the architecture with SystemC. EEMBC and SNORT was used to measure L2-4 and L7 processing time. When multimedia traffic was entered into the network processor in the same flow, the proposed architecture showed about 85% higher performance than general architecture.