• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.649-651
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• 2004

본 논문은 메모리 집적도의 증가로 인해 많이 발생하는 이웃 패턴 감응 고장에 대한 효율적인 테스팅 방법을 제안하고 있다. 기존의 테스팅 방법에서는 비트 단위의 순차적인 셀 어레이 접근으로 인해 결함 검출율과 테스팅 시간에 있어서 문제를 가지고 있다. 이러한 문제들을 본 논문에서는 이웃 패턴 감응 고장을 효율적으로 검출 할 수 있는 타일 방식으로 셀 어레이를 구분하여 이웃 셀의 영역을 제한한다 그리고 기본 셀과 이웃 셀에 필요한 패턴을 병렬로 입출력시킬 수 있는 병렬 접근 디코더와 검출기를 설계함으로써 전체 테스팅 시간을 줄이고 결함 검출율을 높일 수 있는 방법을 제안한다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1038-1045
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• 1994

In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

• Journal of KIISE:Software and Applications
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• v.27 no.2
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• pp.108-119
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• 2000

Most of prior works on testing parallel programs have concentrated on how to guarantee the reproducibility by employing event traces exercised during executions of a program. Consequently, little work has been done to generate meaningful event sequences, especially, from specifications. This paper describes techniques for deriving event sequences from Message Sequence Charts(MSCs) which are widely used in telecommunication areas for its simplicity in specifying the behaviors of a program. For deriving event sequences from MSCs, we have to uncover the causality relations among events embedded implicitly in MSCs. In order to attain this goal, we adapt vector time stamping which has been previously used to determine the ordering of events taken place during an execution of interacting processes. Then, valid event sequences, satisfying the causality relations, are generated according to the interleaving rules suggested in this paper. The feasibility of our testing technique was investigated using the phone conversation example. In addition, we discussed on the experimental results gained from the example and how to combine various test criteria into our testing environment.

• Journal of KIISE:Software and Applications
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• v.27 no.6
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• pp.607-617
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• 2000

Concurrent programs, which are composed of threads that can operate concurrently, are intrinsically nondeterministic. Therefore, we can not directly apply classical testing or debugging techniques developed for sequential programs to concurrent programs because of the nonreproducibility due to nondeterminism. In this paper, we present a source tranformation method to guarantee the reproducibility of multi-threaded programs written in Java programming language. Once a mutli-threaded program has been transformed according to the transformation rules, we can force the program's execution to follow the given sequence of synchronized methods repeatedly and reduce the efforts to find the source of the errors. In addition, we present a method for checking the feasibility of the synchronized method sequence to be replayed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.7
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• pp.666-676
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• 1992

In this paper, algorithm and testable circuit to find all PSF(Pattern Sensitive Fault ) occured in RAM were proposed. Conventional test circuit and algorithm took much time in testing because consecutive test for RAM cells or f-dimensional memory struciure was not employed. In this paper, methodology for parallel RAM-testing was proposed by compensating additional circuit for test to conventional RAM circuit. Additional circuits are parallel comparator, error detector, group selector circuit and a modified decoder used for parallel testing. And also, the constructive method of Eulerian path to obtain efficient test pattern was performed. Consequently, If algorithm proposed in this paper Is used, the same operations as 32sxwor4 lines will be needed to test b x w=n matrix RAM. Circuit simulation was performerd, and 10 bits x :If words testable RAM was designed.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.135-149
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• 2000

Most of prior works on testing parallel programs have concentrated on how to guarantee the reproducibility by employing event traces exercised during executions of a program. Consequently, little work has been done to generate test cases, especially, from specifications produced from software development process. In this research work, we devise the techniques for deriving test cases automatically from the specifications written in Message Sequence Charts(MSCs) which are widely used in telecommunication areas and develop the testing environment for performing module testing of parallel programs with derived test cases. For deriving test cases from MSCs, we have to uncover the causality relations among events embedded implicitly in MSCs. For this, we devise the methods for adapting vector time stamping to MSCs, Then, valid event sequences, satisfying the causality relations, are generated and these are used as test cases. The generated test cases, written in TTCN, are translated into CHILL source codes, which interact with a target module to be tested and test the validity of behaviors of the module. Since the testing method developed in this research work extracts test cases from the MSC specifications produced front telecommunications software development process, it is not necessary to describe auxiliary specifications for testing. In audition adapting vector time stamping generates automatically the event sequences, the generated event sequences that are ones for whole system can be used for individual testing purpose.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1987-1994
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• 1997

ATM switching software should be required high reliability, functionality, extendability and maintainability. After development of the software, it is verified and tested by analyzer whether the software is accomplished the characteristics of it or not. There are so many CASE tools in other area, but the CHILL testing tools that can verify ATM softwares have not various functions are not many. In this paper we develop the testing tool which can evaluate and test CHILL programmed ATM software. This Tool supports testing reports, debugging informations and maintenance informations including parallel process about CHILL original programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.999-1010
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• 2003

Program slicing is s method to extract the statements from the program which have an influence on the value of a variable at a paricular point of the program. Program slicing is applied for many applications, such as program degugging, program testing, program integration, parallel program execution, software metrics, reverse engineering, and software maintenance, etc. This paper is the study to create the exact slice in the presence of Object Reference State Graph to generate more exactly static analysis information of objects in the program of the presence of complicated data structure.