• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.103-108
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• 2016

In communication systems the solution of the problem of maximizing the mutual information between the input and output of a channel composed of several subchannels under total power constraint has a waterfilling structure. OFDM and MIMO can be decomposed into parallel subchannels with CSI. Waterfilling solves the problem of optimal power allocation to these subchannels to achieve the rate approaching the channel capacity under total power constraint. In waterfilling, more power is alloted to good channels(high SNR) and less or no power to bad channels to increase the rate of good channels, resulting in channel capacity. Waterfilling finds the exact water level satisfying the power constraint employing an iterative algorithm to estimate and update the water level. In this process computation of partial sums of inverse of square of subchannel gain is repeatedly required. In this paper we reduced the computation time of waterfilling algorithm by replacing the partial sum computation with reference to an array which contains the precomputed partial sums in initialization phase.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.21-30
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• 1999

Several kinds of design method for the hairpin type band-pass filter have been reported. The conventional design methods have some restrictions in characteristic impedance of coupled line section, which provide complexities to designer. In this paper, the novel design formulas for the hairpin type band pass filter have been derived and proposed to resolve the problems of the reported design methods. By employing the equivalent circuit of the coupled line section and band pass filter design theory, the design procedures and formulas are derived. The hairpin type RX/TX band pass filters for the IMT-2000 service have been designed, fabricated with duplexer configuration, and then measured to show the validity of the proposed design method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.32-39
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• 2009

In this thesis, design effective elimination interference algorithm of ICS repeat system for repeater that improve frequency efficiency. Gennerally, LMS Algorithm apply to ICS repeat system. Error convergence speed and accuracy of LMS Algorithm are influenced by reference signal. For improve LMS Algorithm, suggest Adaptive searching channel estimate algorithm. For using channel characteristic, adaptive searching channel estimate algorithm make reference signal similar interference signal by convolution operation and complement LMS algorithm demerit. For make channel similar pratical channel, apply Jake's Rayleigh multi-path model. LMS algorithm and suggested adaptive searching channel estimate algorithm that have 16 taps apply to ICS repeat system under Rayleigh multi-path channel, so simulate with MATLAB. According to simulate, ICS repeat system with LMS algorithm show -40 dB mean square error convergent after 110 datas iteration and ICS repeat system with adaptive searching channel estimate algorithm show -80 dB mean square en-or convergent after 120 datas iteration. Analyze simulation result, suggested adaptive searching channel estimate algorithm show 40 dB accuracy than LMS algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.22-29
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• 2009

In this paper, we developed the 200-Watts SSPA(Solid State Power Amplifier) for the X-band pulse compression solid state radar. The developed X-band SSPA is consists of 3-stage CSA(Corporate Structured Amplifier) modules in pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main-power amplifier stage of SSPA designed by balanced type using GaN HEMT with enough power and gain to generate power more than 200-Watts in X-band. The developed SSPA has performance with more than total gain 59dB and output power 200-Watts in condition of frequency range 9.2-9.6GHz, pulse period 1msec, pulse width 100usec and duty cycle 10%. The developed SSPA in this paper can apply to high quality solid state radar system with pulse compression technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• KIISE Transactions on Computing Practices
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• v.20 no.10
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• pp.534-542
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• 2014

Multiscale modeling is a new simulation approach which can manage different spatial and temporal scales of system. In this study, as part of multiscale modeling research, we propose the way of combining two different simulation methods, molecular dynamics(MD) and stochastic rotation dynamics(SRD). Our conceptual implementations are based on LAMMPS, one of the well-known molecular dynamics programs. Our prototype of multiscale modeling follows the form of the third party implementation of LAMMPS. It added MD to SRD in order to simulate the boundary area of the simulation box. Because it is important to guarantee the seamless simulation, we also designed the overlap zones and communication zones. The preliminary experimental results showed that our proposed scheme is properly worked out and the execution time is also reduced.

• Journal of Korea Multimedia Society
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• v.16 no.5
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• pp.657-666
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• 2013

Today, many aspects of our lives are characterized by the rapid influx of large amounts of data from various application domains. The applications that produce this massive of data span a large spectrum, from social media to business intelligence or biology. This massive influx of data necessitates large scale parallelism for efficiently supporting a large class of analysis tasks. Recently, there have been extensive studies in using MapReduce framework to support large parallelism. While this technique has produced impressive results in diverse applications, the same can not be said for multimedia applications where most of users are interested in a small number of results having high or low score. Thus, in this paper, we develop the data partitioning algorithm which is able to efficiently process large data set having different data utility. The experiment results show that the proposed technique provides significant execution time gains over the existing solution.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• Journal of computational fluids engineering
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• v.18 no.1
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• pp.83-90
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• 2013

OpenMP is becoming more and more useful as a simple parallel processing paradigm on SMP (Shared Memory Multi-Processors) computing environment with the development of multi-core processors. However, very few data is available publically regarding the OpenMP performance in CFD (Computational Fluid Dynamics). In the present study a CFD test suite is prepared for the performance evaluation of OpenMP on various multi-core systems. The test suite is composed of two-dimensional numerical simulations for inviscid/viscous and reacting/non-reacting flows using three different levels of grid systems. One to five test runs were carried out on various systems from dual-core dual threads to 16-core 32-threads systems by changing the number of threads engaged for each test up to 80. The results exhibit some interesting results and the lessons learned from the tests would be quite helpful for the further use of OpenMP for CFD studies using multi-core processor systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.4
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• pp.352-357
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• 2000

The vector control scheme is usually applied to the high performance induction motor drives. The PI controller is adopted traditionally to control the motor speed and currents in the vector control scheme. In this case, the dynamic performance of the induction motor is dependent on the PI gains and the gain optimization is necessary in order to get a good dynamic performance. But, it is very hard to optimize the PI gains uniquely within the speed control range because the equivalent model of the motor control system should be known exactly. In this paper, we propose the hybrid control scheme to remove the defects of PI controller. The hybrid control scheme includes the simplified fuzzy controller which operates in the transient state and the PI controller which operates in the steady state. The proposed scheme is applied to the vector control for induction motor, and the digital simulation and the experimental results are given to verify the proposed scheme.