• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.5
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• pp.29-36
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• 2004

This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.102-109
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• 2003

In this paper, the new multiplicative algorithm using standard basis over GF(2m) is proposed. The multiplicative process is simplified by data select method in proposed algorithm. After multiplicative operation, the terms of degree greater than m can be expressed as a polynomial of standard basis with degree less than m by irreducible polynomial. For circuit implementation of proposed algorithm, we design the circuit using multiplexer and show the example over GF(24). The proposed architectures are regular and simple extension for m. Also, the comparison result show that the proposed architecture is more simple than privious multipliers. Therefore, it well suited for VLSI realization and application other operation circuits.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.749-755
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• 2003

Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.38-49
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• 1994

This paper proposes Echo canceller used in simultaneous two-way ('full-duplex') transmission of data signals over two-wire circuits which can be achieved by using a hybrid coupler. This Echo canceller uses sequential processing instead of parallel processing with conventional adaptive digital filter. This structure reduces the number of multipliers. Thus, this structure is much more suitable for IC implementation. This Echo canceller operates according to the 'Stochastic Iteration Algorithm(SIA).' SIA algorithm has merit of good performance and small hardware requirement.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.39-41
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• 1999

최근의 보편적인 컴퓨터 응용분야인 컴퓨터 그래픽, 패턴인식, 음성 출력 등과 같은 제분야에서는 대용량의 데이터를 실시간으로 처리하는 것이 필수적이다. RNS는 캐리부재, 병렬처리 등의 특징을 가지므로 대용량 데이터의 실시간 처리를 지원하는 장치의 개발에 큰 이점이 있다. 본 논문에서는 RNS에서 웨이티드 수체계로 변환하는 방법을 유도하고 구현한다. 이 방법은 연산의 비트수가 증가하더라도 고정된 연산의 단계를 거치게 되고, 여기에서 이 방법의 효율성이 커진다. 이는 중첩 비트 주사기법을 CRT 변환시에 적용하는 새로운 방법이다. 그리고, 변환식의 유도와 실제 시뮬레이션의 결과를 타 시스템과 비교하여 본 논문의 방법이 타당함을 보여준다. 그 결과, 기존의 승산기보다 많은 하드웨어를 요구하지만, 이는 최근의 반도체 집적기술의 발전으로 인하여 큰 문제가 되지 않고, 반면에 병렬 t행과 캐리 부재의 특성으로 인해 기존의 방법보다 속도를 향상시킬 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1017-1021
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• 2005

현대에 있어서 영상정보는 아주 큰 비중을 차지하고 있다. 따라서 이러한 영상정보를 얼마나 빨리 그리고 많이 압축 시킬 수 있는가가 핵심적인 관건이다. 본 논문에서는 공간적 압축 방식의 핵심인 DCT와 비교하여 블록킹 효과(Blocking Effect)과 없고, 우수한 압축 성능을 갖는 DWT(Discrete Wavelet Transform)알고리즘을 적용한 2차원 이산 웨이브렛 변환 필터를 설계하였다. 본 논문에서 구현한 DWT 필터는 FIR필터 방법으로 설계하였으며, Daubenchies-4 Tap을 이용하였고, 파이프라인 연산으로 승산기, 가산기를 병렬로 처리하여 고속연산을 수행하였다. 뿐만 아니라 메모리 맵핑 과정과 메모리 컨트롤 어드레스 발생기를 사용하여 메모리와 연산량을 최소화 하여 칩사이즈를 줄여 설계하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.