• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.373-381
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• 2017

Kyeonggi Provincial Government is considering double decker bus service to solve the problem of heavy rush hour traffic. However, the height-to-width ratio is more than 1.16 times larger than that of a general high-speed single decker bus, and the center of gravity is higher. This could cause driving stability problems, such as turnover and breakaway from the lane, especially under strong side-wind conditions at high speed. In this numerical study, the driving characteristics of a model double decker bus were reviewed under side-wind and superelevation conditions at high driving speed. The rolling, pitching, and yawing moment of the model bus were calculated with CFD numerical simulation, and the results were compared to the recovery angular moments of the model bus to evaluate the dynamic stability under given driving conditions. As the model vehicle moves on a straight level road, it is stable under any side-wind conditions. However, on a curved road under side-wind conditions, it could reach unstable conditions dynamically. There is a chance that the bus will turn over when it moves on a curved road with a radius of gyration less than 100 m under side-wind (15 m/s). However, there is a very small chance of breakaway from the lane under any driving conditions.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.5
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• pp.108-126
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• 2023

In this paper, the dynamic hard shoulder running for bus only (HSRFBO) was presented to solve the traffic congestion by increase the capacity in chronic congested sections of highways, and a simulation was performed to evaluate the comparison with the current hard shoulder running for all vehicles(HSRFAV) and median bus only lane and HSR(MBOLHSR). According to the evaluation results, it was evaluated to be more advantageous in terms of traffic flow and safety than the current HSRFAV. In addition, the speed of passing buses is slightly reduced compared to the MBOHSR, but the speed of entering and exiting buses is increased and the speed of buses and cars is greatly improved. Therefore It was analyzed that the efficiency of transport personnel was also improved. In particular, it is expected that traffic flow will be stabilized as the difference in speed between passenger cars and buses will be greatly reduced, and violations of exclusive bus lanes by passenger cars will be greatly reduced. In addition, the operation time of HSR is greatly reduced, so that the original function of the shoulder lane can be maintained as much as possible. As a result, it was analyzed that the risk of accidents was significantly reduced when operating HSRFBO compared to when operating MBOHSR, and cross-conflicts with high accident severity did not occur.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.582-594
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• 2016

Most studies on hybrid buses are on large-sized buses and not mid-sized low-floor buses. This study uses MATLAB simulation to evaluate the fuel efficiency of such buses powered by diesel. Based on the results, a hybrid electric vehicle system is recommended for the best combination of power and gear ratio. A parallel hybrid system was selected for the hybridization, which transmits front and rear wheel power independently. The necessary power to satisfy the target performance was calculated, and the applicable capacity area was designed. Dynamic programing was used to create and optimize a component sizing algorithm, which was used to scale the capacity of each component of the power source to satisfy the design criteria. The fuel efficiency rate, optimum power source capacity, and gear ratio can be improved by converting a conventional bus into a parallel hybrid bus.

• Journal of the Korea Society of Computer and Information
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• v.27 no.1
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• pp.141-148
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• 2022

Global climate change caused by greenhouse gases(GHG) is getting serious. To prevent this, countries around the world are regulating GHG emissions. Korea has decided to reduce GHG emissions by 37% compared to BAU (Business As Usual) by 2030. The transportation sector accounted for 18.58% of the domestic GHG emission, and roads accounted for 93.75% of the total. Public transportation is also included in the target of GHG reduction, and this study was conducted to reduce GHG emissions of bus public transportation, which can reduce GHG emissions while reducing the cost of road transportation. In this study, a simulation was conducted to predict the optimal GHG emission compared to the waiting time of passengers by adjusting the bus dispatch interval by implementing a greenhouse gas simulation model using Any Logic. If a more precise model is implemented in the future, it is expected that it will be used to reduce bus GHG emissions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.22-31
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• 1989

In this paper, we analyze the performance of the IEEE 802.4 token passing bus protocol through a simulation model of the protocol. In order to analyze performance of the protocol in the initialization, transition and fault recovery states as well as in the steady state, the protocol functions are divided into five processes each of which can effectively simulate protocol behaviors according to the variations of protocol parameters. From the simulation study, we obtain protocol parameters which severely influence the protocol performance and find out that proper selection of the protocol parameter values for token passing is very important to obtain good performance of the protocol when the priority scheme is used.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.

• Journal of the Korean Institute of Landscape Architecture
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• v.51 no.4
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• pp.16-30
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• 2023

As the concept of metaverse has received great attention, interest in metaverse related to landscape architecture is also increasing. The aim of this research is to understand the potential and tasks of applying metaverse in the field of landscape architecture by analyzing the user experience of a metaverse platform. The object of the research is Meta-Everland built in the Roblox platform, which has the most users among landscape architectural metaverses in Korea. NPS of 30 users who have been to Everalnd was investigated after using Meta-Everland with interviews. NPS before the metaverse experience was -16 and NPS after the experience was -24. This result means that the promotion level was lowered after the experience of the metaverse. There were three causes of lowered NPS: lack of users, low-quality graphics and interface, and lack of content. The factor of lack of users was the result of the other two problems. The factor of low technical quality is hard to be improved in a short period of time. Therefore, the main task to improve the metaverse is developing better metaverse content related to landscape architecture. It is more appropriate to develop metaverse-specific content rather than improve reality issues. Applying AR and VR devices, enhancing communication function, and developing potential as a simulation device are needed to be considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.30-32
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• 1998

멀티프로세서 시스템을 설계할 경우에는 공유메모리 구조와 메시지 전달방법의 두 가지의 패러다임을 바탕으로 하게 된다. 데이터 분할과 동적 부하 분산 문제를 단순화시틸 수 있으며 확장성을 용이하게 지원하는 장점을 가지고 있는 공유메모리 구조의 멀티프로세서 시스템에서 각 프로세서가 자신의 전용 캐시를 가지는 경우에는 메인 메모리와 이러한 전용 캐시내에 존재하는 데이터사본간에 일관성 문제가 발생한다. 본 논문에서는 일관성 유지를 위해 제안되어 있는 여러 알고리즘 중 처리 노드와 고대역 저지연 인터커넥션 네트워크로 구성되는 공유메모리 구조의 멀티프로세서 프로토타입인 DASH 프로토콜을 지원하기 위한 전용 버스 시스템을 완전 개방형인 IEEE Futurebus+ 스탠다드에 준비하여 설계한 다음, 이 시스템이 DASH 프로토콜을 지원하려 캐시의 일관성을 유지하기 위해 필요한 각종 행동과 기존의 범용 버스 시스템이 수행하는 행동의 병렬 처리를 지원할 수 있음을 시뮬레이션으로 증명한다.