• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.122-131
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• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.809-812
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• 2013

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of the Korea Society of Computer and Information
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• v.11 no.1 s.39
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• pp.157-165
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• 2006

This paper proposes a new output-buffered multicast ATM switch with tandem crosspoints switching fabric, named the MTCOS(Multicast Tandem Crosspoint Output-buffered Switch). The MTCOS consists of multiple simple crosspoint switch fabrics, named TCSF(Tandem Crosspoint Switch Fabric) , and concentrated output buffers for efficient multicasting. The TCSF resolves the cell delay deviation problem which the self-routing crossbar switches inherently have. Further, it offers multiple concurrent pathes from one input to multiple output ports. It also provides multi-channel switching by easy software configuration and has several desirable characteristics such as scalability, high Performance, and modularity. A shared traffic concentration and output queuing strategies of the MTCOS results in lower cell loss as well as lower cell delay time over a wide range of multicast traffic. Furthermore, it has lower hardware complexity than that of the SCOQ and Knockout multicast switch to achieve the same Knockout concentration rate as the conventional switches. It is shown that the proposed switch can be easily applied to design high performance for any multicast traffic by analytic analysis and computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.60-67
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• 2008

This paper presents a new full-bridge soft switching PWM DC-DC converter circuit topology that adding two switcher, two lossless snubber quasi-resonance capacity, two diode to power source for general welding machine. This half bridge soft switching Is low voltage hight current output that first coil current is smaller than second coil current in high frequency transformer can be obtained with decreasing path loss in conventional DC bus line switcher. As it operate ZCS/ZVS in full range, high frequency, high efficiency and high output are implemented at low voltage and high DC current switching power supplies. All of this items are got from simulation and the result of experiment. If make up for the weak points of this proposed circuit, it will be used more easily for next generation TIG, MIG and MAG type of arc-welding machine.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.1
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• pp.82-90
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• 2013

In this paper, conducted emission from the MDS(Motor Drive System) of a HEV/EV was analyzed using high- frequency circuit modeling in system-level approach. The conducted emission by PWM process can cause RFI(radio- frequency interference) problems in the AM/FM frequency range. In order to mitigate this conducted emission, a high-frequency equivalent circuit model is proposed by analyzing the fundamental circuits, parasitic components in their parts and connections and non-linear characteristics of IGBTs, high-power capacitors, inverters, motors, high-power cables, and bus bars which are composed of the MDS. It is confirmed that the simulated result by the proposed model is well agreed with measured results in spite of a large-scaled analysis in system level. We are looking forward that this approach can be effectively used in the EMC design of HEV/EV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1413-1421
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• 2014

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.95-103
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• 2002

We know that the all of warfare system has been becoming complex and variety in warfield thru the Gulf-War. The all of warfare electronic systems is designed to inter-operate by networks in recently. Especially Warfare Equipment systems of Men-of-War(War ship) as like KDX(Korea Destroyer, Experimental), FF(Frigate), PCC(Costal Patrol Craft), Submarine are connected by Combat System Databus to the Command system(C2 System), so C2 system can control all of equipments in ship. In this view, the status of network(Combat System Databus) is very critical parameter in war field. So In this paper, we propose the method of Network Management System construction for War ship, and especially propose the architectural design of network management system for DX(Destroyer, Experimental) equipments using SNMP(Simple Network Management Protocol). And Link Utilization is monitored by simulation. 

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.586-594
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• 2003

X-Match algorithm is a lossless compression algorithm suitable for hardware implementation owing to its simplicity. It can compress 32 bits per clock cycle and is suitable for real time compression. However, as the bus width increases 64-bit, the compression unit also need to increase. This paper proposes the cooperative parallel X-Match (X-MatchCP) algorithm, which improves the compression speed by performing the two X-Match algorithms in parallel. It searches the all dictionary for two words, combines the compression codes of two words generated by parallel X-Match compression and outputs the combined code while the previous parallel X-Match algorithm searches an individual dictionary. The compression ratio in X-MatchCP is almost the same as in X-Match. X-MatchCP algorithm is described and simulated by Verilog hardware description language.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.63-72
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• 2020

As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.