• Proceedings of the Korean Society of Computer Information Conference
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• 2024.01a
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• pp.431-432
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• 2024

본 논문에서는 오락실 메타버스를 구축하도록 한다. 구축은 젭 맵 에디터를 이용하고 스폰을 생성하며 아이코그램스를 이용하여 설계하도록 한다. 오락실 메타버스는 주차장, 오락실 1, 오락실 2, 그리고 휴게실을 각각 구축하도록 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.88-97
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• 1990

In this paper, DPA bus is proposed for implementation of MC 68000 based tightly-coupled multiprocessor system. The DPMC and arbiter are designed that the local memory of each PE can accept memory request both from a local processor and from the system bus. The performance of the proposed system bus is evaluated by Stochastic Petri Net(SPN) system modeling. The processing power, the efficiency, and the utilization of system bus are simulated for various load factors.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.07a
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• pp.319-320
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• 2020

본 논문에서는 스마트 폰의 GPS 센서와 Google Map, OPEN API 기반의 버스 정보 제공을 하며 연동이 자유로운 어플리케이션을 설계하고 구현한다. 이 어플리케이션은 안드로이드의 GPS센서를 이용하여 현재 사용자의 위치를 기준으로 반경 200m 안의 버스 정류장을 확인할 수 있다. 그리고 공적마스크를 판매하는 약국/농협/우체국의 위치를 확인할 수 있다. 또한, 사용자의 위치 주변이 아닌 곳의 버스와 정류장을 검색할 수 있고 내릴 정류장 혹은 위치를 저장하여 내리기 전 알람을 받을 수 있다.

• Bulletin of the Korean Space Science Society
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• 2006.10a
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• pp.109-109
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• 2006

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.288-299
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• 1993

This paper proposes the new bus protocol in the tightly coupled multiprocessor system. The bus protocol uses the pipelined data transfer and block transfer scheme to increase the bus bandwidth, The bus also has the independent transfer lines for the address and data respectively, and it can transfer the data up to maximum 264 Mbytes /sec. This paper also models the multiprocessor system where each processor boards have the private cache. Simulation evaluates the bus and system performance according to hit ratio of the reference data in cache memory, In the case of using this bus, the bus is evaluated not to be saturated when up to 10 processor boards are connected to the bus. As for up to 4 memory interleavng, the performance increases linearly.

• Journal of Korea Game Society
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• v.22 no.1
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• pp.65-76
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• 2022

What difference does the metaverse experience have from the real world? This study investigated the effect of space size and dialogue topic on metaverse user experience. The results from a 3(space size: reality vs. metaverse in an open room vs. metaverse in a closed room) x 2(dialogue topic: positive vs. negative) mixed factorial design experiment (N = 75) revealed statistically significant effects of space on responsiveness, and dialogue topic on closeness. This result implies that designing metaverse for non-immersive devices should include careful considerations regarding the characteristics of the user's real space.

• Journal of Astronomy and Space Sciences
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• v.20 no.4
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• pp.339-350
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• 2003

Engineering qualification model payload for a communications and broadcasting satellite(CBS) was developed by ETRI from May, 2000 to April, 2003. For. the purpose of functional test and verification of the payload, a real-time hardware-in-the-loop(HITL) CBS simulator(CBSSIM) was also developed. We assumed that the spacecraft platform for the CBSSIM is a geostationary communication satellite using momentum bias three-axis stabilization control technique based on Koreasat. The payload hardware is combined with CBSSIM via Power, Command and Telemetry System(PCTS) of Electrical Ground Support Equipment(EGSE). CBSSIM is connected with PCTS by TCP/IP and the payload is combined with PCTS by MIL-STD-1553B protocol and DC harness. This simulator runs under the PC-based simulation environment with Windows 2000 operating system. The satellite commands from the operators are transferred to the payload or bus subsystem models through the real-time process block in the simulator. Design requirements of the CBSSIM are to operate in real-time and generate telemetry. CBSSIM provides various graphic monitoring interfaces and control functions and supports both pre-launch and after-launch of a communication satellite system. In this paper, the HITL simulator system including CBSSIM, communications payload and PCTS as the medium of interface between CBSSIM and communications payload will be described in aspects of the system architecture, spacecraft models, and simulator operation environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.343-350
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• 2016

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.239-240
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• 2012

ITER 초전도자석 전원공급장치는 대전류를 흘리기 위한 자체 지지구조 버스바와 이를 지지하기 위한 구조물로 구성된다. 장치설계에 있어 버스바와 지지구조물은 단락 시 전자기력에 대한 내성, 통전전류에 의한 버스바 발열 등의 요구조건을 만족하여야 한다. 본 논문은 ITER 초전도자석 전원공급장치에 유한요소해석을 적용하여 여러 요구조건에 부합하는 설계의 적합성을 검증한다.