• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1996.10a
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• pp.725-727
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• 1996

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.193-196
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• 1999

본 논문은 음향 임펄스를 모델링하는데 코사인 변조된 필터 뱅크와 Decimation을 이용하여 수렴 속도를 개선하는 방법을 제안하고 이를 잡음제거에 응용하였다. 제안된 구조는 입력신호를 필터뱅크를 이용하여 각 서브밴드로 분할한 후 필터 입력신호의 고유벡터의 최대값과 최소값의 비를 줄이고 필터의 탭수를 줄이기 위해서 decimation을 행한다. 그리고 서브밴드대역의 샘플링 주파수를 낮추어 신호 스펙트럼을 확장시켜 이를 적응필터에 입력하여 수렴속도를 향상시켰다. 실험 결과, Colored잡음의 경우 LMS 알고리즘보다 제안된 방법이 MSE(Mean Square Error)는 좋지는 않았다. 실제 음향시스템의 모델링에는 거의 같은 MSE을 갖으며, 수렴 속도에는 모두 빠른 성능을 보였으며, 이를 음질향상에 적용하여 향상된 음질을 얻을 수 있었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1345-1347
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• 2015

본 논문에서는 응급상황이 신고되는 상황에서 수보자에게 전달되는 신고자의 주변음향신호로부터 신고자의 주변상황을 추정하기 위하여 음향의 주파수적 특성 및 변화특성의 모델링 성능이 뛰어난 Gabor 필터뱅크 기반의 특징벡터 추출 기술 및 분류 성능이 뛰어난 심화신경망을 도입한다. 제안하는 Gabor 필터뱅크 기반의 특징벡터 추출 기법은 비음성 구간 검출기를 통하여 음성/비음성을 구분한 후에 비음성 구간에서 23차의 Mel-filter bank 계수를 추출한 후에 이로부터 Gabor 필터를 이용하여 주변상황 추정을 위한 특징벡터를 추출하고, 이로부터 학습된 심화신경망을 통하여 신고자의 장소적 정보를 추정한다. 제안된 기법은 여러 가지 시나리오 환경에서 평가되었으며, 우수한 분류성능을 보였다.

• Journal of the Society of Naval Architects of Korea
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• v.32 no.2
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• pp.68-74
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• 1995

The statistical analysis system is necessary to predict the resistance and powering performance quickly and precisely at the initial design stage. The authors propose the several functions of the performance prediction program and the structures of data bank. The program includes several series charts, regression coefficients and adapted regression analysis method based on the data bank to predict the resistance and propulsive coefficients. The calculation procedure to find out the principal dimensions and open-water efficiency of the optimum propeller is also included. The evaluation for the program and data bank is conducted by the arbitrarily selected 14 ship models. The results show good agreement with experiments within 5% mean prediction error.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.69-78
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• 2009

One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.556-563
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• 2002

In this paper, a novel method for designing an M-channel, causal, stable IIR cosine-modulated filter bank (CMFB) with near PR property is proposed. The IIR prototype filter is designed with a simple constraint using lattice stucture with 1st order allpass filter components. The IIR prototype filter which is designed by the proposed method has higher stopband attenuation and sharper roll-off characteristic than the one which is designed by the previously proposed method with similar complexity. The proposed M-channel IIR CMFB which is designed from this IIR prototype filter is applied to subband acoustic echo canceller (AEC). We obtained about 15dB higher ERLE using this subband AEC than when M-channel FIR subband AEC with similar complexity.

• The Journal of the Acoustical Society of Korea
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• v.17 no.5
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• pp.57-62
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• 1998

본 논문에서는 입력신호의 시변특성에 따라 분석 필터의 대역을 가변 시키는 필터 뱅크의 구조를 제안한다. 제안된 필터뱅크는 일반적으로 32개의 균일한 대역으로 나누어 임 계대역의 표현을 적절히 표현하지 못하는 Polyphase 필터의 단점을 극복하면서 시스템 설 계에 높은 계산량을 요구하는 QMF-tree 필터의 단점을 보완한다. 본 연구에서는 분할 대역 은 4개에서 26개의 대역으로 가변하고, 웨이블릿 필터중 Daubechies필터를 사용하였다. 제 안된 구조의 부호화기는 128kbps에서 MPEG-a오디오와 비슷한 수준의 CD 음질을 유지하 며, 연산량 비교결과는 PolyPhase filter를 이용한 MPEG보다 부호화, 복호화 과정을 합쳐 다양한 전송률과 음원에서 평균 19%의 감소를 얻었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.40-42
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• 2014

최근의 컴퓨터 시스템은 멀티 코어를 기반으로 병렬성 향상을 추구 하고 있지만 코어의 개수가 증가함에 따라 메모리가 새로운 병목 지점으로 지적되고 있다. 메모리 시스템은 가상 메모리, 물리 메모리, 뱅크 메모리 3계층으로 나눌 수 있으며, 각 계층은 상호연관 관계가 있어서 분석하기에 어려움이 있다. 본 논문에서는 이를 위해 계층 구조를 지원하는 시뮬레이터를 제안한다. 제안하는 시뮬레이터는 총 5개의 구성 요소로 이루어져 있으며, CPU 개수, 캐시 정책, 뱅크 개수등 다양한 설정을 지원한다. 또한 시뮬레이터를 통하여 운영체제 수준의 물리 메모리 관리자가 메모리 접근 지연에 영향이 있음을 보인다.