• Information Display
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• v.16 no.5
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• pp.3-10
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• 2015

• Information and Communications Magazine
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• v.9 no.4
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• pp.31-39
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• 1992

• Polymer Science and Technology
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• v.18 no.2
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• pp.167-172
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• 2007

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1056-1064
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• 2010

This paper presents the approximate analysis method for the symmetric transmission line crossing the aperture in an backplane. The method of moments is used to determine the aperture impedance for the construction of the equivalent transmission line that the aperture impedance apply to the transmission line as the shunt impedance. As the results, the insertion loss increases at the specific frequency range for the impedance matching. In the case of the mismatching, we are confirmed to the insertion gain at the specific frequency. Also the horizontal length of the aperture affects to the transmission line better than vertical length. The measurement of the insertion loss is performed to verify the theoretical analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.46-55
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• 2014

PCB design technology for high-speed transmission line has been developed continuously. Adapting to the high capacity of the communication system, switch fabric interface used for backplane is being standardized to accommodate more than 10Gbps serial interface. In this paper, various computer simulations are performed to compare the performance of each transmission line per length according to PCB material, and also to analyze the effect from via stub length and crosstalk, for the purpose of applying 11.5Gbps serial interface as a switch fabric interface in tera-bit switching system. As a result of the simulation, important design issues, such as PCB material of each board supporting 8dB improvement in transmission loss using low loss PCB, maximum available stub length on transmission line via, whether or not to apply the backdrill process to the via, and the clearance of the differential pair between transmission lines, are determined. The most efficient system architecture which could be applied 11.5Gbps serial interface in all switch fabric interfaces is defined from the simulation results.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.275-278
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• 2000

As the operating frequency of digital modules in network system becomes fast, integrity of signals between modules is regarded as a important factor in high speed system design. To guarantee the signal integrity, many factors that deteriorate quality of signal should be considered. In this paper, we survey many factors which be considered while in designing and imp]ementing the backplane for high speed router and analyze the simulation result and experimental result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.

• Electronics and Telecommunications Trends
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• v.25 no.5
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• pp.33-46
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• 2010

인쇄전자회로 기술은 인쇄(graphic art printing) 공정을 활용한 다양한 광/전자 기기 개발을 위한 핵심요소 기술이다. 기능성 전자 잉크 소재와 초저가격의 프린팅 공정을 통해서 유비쿼터스 시대의 차세대 모바일 IT 기기의 생명력을 불어넣게 된다. 현재 기술 수준이 일부 요소 부품들을 제작하고 기본 단위의 정보처리를 가능케 하는 수준에 머무르고 있으나, 여러 가지 잉크 소재 및 다양한 초미세 인쇄 공정 기술의 개발이 진행됨에 따라 향후 폭넓은 분양에 적용될 것으로 기대된다. 궁극적으로 인쇄전자회로의 성능이 향상되고 고집적화 됨으로써 기존의 Si 기반 CPU나 IC 칩을 대체하는 공정으로 자리매김을 할 것으로 예상된다. 본 기고문에서는 이러한 인쇄전자회로 기술 및 동향에 대해 기술하였다. 특히, 현재 폭넓게 연구가 진행중인 차세대 디스플레이 백플레인이나 개별물품단위 트래킹을 위한 플라스틱 RFID 태그 적용을 위해 필요한 요건들을 인쇄전자회로 기술관점에서 조망하였다.

• Electronics and Telecommunications Trends
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• v.23 no.2 s.110
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• pp.130-141
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• 2008

본 OTH 스위치패브릭 구성방안은 OTN 망에서 다양한 클라이언트 신호를 수용하기 위한 요구사항을 기반으로 소용량에서부터 320G급 이상의 대용량까지 차세대 전송망에서 다양한 기능과 경쟁력을 갖추기 위한 OTH 스위치패브릭 구성방안을 고찰하였다. OTH 망에서 리던던시 구조 및 입출력 포트 요구조건의 설정에 따라 망 구성 및 시스템 설계를 할 수 있도록 스위치패브릭을 구성하는 방안을 제시하였다. 본 고에서는 최근 시스템 플랫폼의 세계 추세로 적용되고 있는 Advanced TCA 기반으로 백플레인 구성방법에 따라 가능한 구조를 고찰하였으며, Advanced TCA 플랫폼 및 이와 경쟁 가능한 동등 이상의 플랫폼 기반에서 적용 가능하다.