• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.18-24
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• 2007

As VLSI technology scales to nano-meter order, relatively increasing global wire-delay has added complexity to system design. Global wire-delay could be reduced by inserting pipeline-elements onto wire but it should be coupled with LIP(Latency Intensive Protocol) to have correct system timing. This combination however, drops the throughput although it ensures system functionality. In this paper, we propose a computation method useful for minimizing throughput deterioration when pipeline-elements are inserted to reduce global wire-delay. We apply this method while placing blocks in the floorplanning stage. When the necessary for this computation is reflected on the floorplanning cost function, the throughput increases by 16.97% on the average when compared with the floorplanning that uses the conventional heuristic throughput-evaluation-method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.11
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• pp.711-717
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• 2017

The railway is a public transportation system that provides large-scale passenger transportation and service, whose reliability and safety is the top priority. The wiring of railway vehicles is classified into train control lines (train lines) and communication lines. The train lines are used for input / output signals related to vehicle driving and safety functions, and the communication lines are used for the input / output signals for passenger services such as broadcasting. In order to measure the reliability of railway vehicles, a train line is applied to the input / output interface of the control signals between the electric control devices in the vehicle, and there are many electromechanical devices such as relays and contactors for the control logic. In fact, since the vehicle control circuit is composed of several thousand contacts, it is difficult to check for errors such as contact failure, and it is impossible to check the real-time status, so a lot of manpower and time is required for regular maintenance. Therefore, we analyze the current state of the train line design of the electric equipment used for driving and services in domestic railway cars and propose three wiring reduction methods to improve it. Based on the analysis of domestic electric vehicles, it was confirmed that the wiring reduction effect is 35% or more.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.74-83
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• 2002

In order to design a huge VLSI system, the scan testing methodology by employing scan flip-flops(cells) is a popular method to test those If chips. In this case, the connection order of scan cells are not important, and hence the order can be determined in the very final stage of physical design such as cell placement. Using this fact, we propose, in this paper, a scan cell reordering method which minimizes the length of wires for scan chain connections. Especially, our reordering method is newly proposed method in the case when the scan cells are grouped according to their clock domains. In fact, the proposed reordering method reduces the wire length about 13.6% more than that by previously proposed reordering method. Our method may also be applicable for reordering scan chains that have various constraints on the scan cell locations due to the chain grouping.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1313-1323
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• 1991

n this thesis CAM(content Addressable Memory) generator and graphic display tool for run-plot sequence in automatic generation of CAM are presented. We show that implementing the layout generation, graphic menu, mouse driver, and data structure by using the basic classes is clear and easy in modification than the conventional procedural language. For the implementation of generator which is independent of design rule or process, we use the parameterized cell so that basic cell can be changed according to user's inputs. and perform the layout by means of placement and routing using pitch mathching. Finally, the display of CIF which generated and constitution of graphic menu for total run-plot sequence are explained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.12-19
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• 1982

In general the design methods of adaptive filter are divided into two categories, one is based upon the local parameter optimization theory and the other is based upon stability theory. Among the various design techniques, the LMS algorithm by steepest-descent method which is based upon local parameter optimization theory is used widely. In designing the adaptive filter, the most important factor is the convergence rate of the algorithm. In this paper a new algorithm is proposed to improve the convergence rate of adaptive firter compared with the commonly used LMS algorithm. The faster convergence rate is obtained by adjusting the adaptation gain of LMS algorithm. And various aspects of improvement of the adaptive filter characteristics are discussed in detail.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.