• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.122-126
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• 2019

These-days technology related to IoT (Internet of Thing) is widely used and there are many types of smart system based IoT like smart health, smart building and so on. In smart health system, it is possible to check someone's health by analyzing data from wearable IoT device like smart watch. Smart building system aims to collect data from sensor such as humidity, temperature, human counter like that and control the building for energy efficiency, security, safety and so forth. Furthermore, smart city system can comprise several smart systems like smart building, smart health, smart mobility, smart energy and etc. In this paper, we propose multimedia IoT based intelligent emergency alarm system for smart city. In existing IoT based smart system, it communicates lightweight data like text data. In the past, due to network's limitations lightweight IoT protocol was proposed for communicating data between things but now network technology develops, problem which is to communicate heavy data is solving. The proposed system obtains video from IP cameras/CCTVs, analyses the video by exploiting AI algorithm for detecting emergencies and prevents them which cause damage or death. If emergency is detected, the proposed system sends warning message that emergency may occur to people or agencies. We built prototype of the intelligent emergency alarm system based on MQTT and assured that the system detected dangerous situation and sent alarm messages. From the test results, it is expected that the system can prevent damages of people, nature and save human life from emergency.

• Journal of IKEEE
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• v.24 no.1
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• pp.161-169
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• 2020

In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the V_TP(Program Threshold Voltage) and the V_TE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and V_T and erase V_T, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.129-134
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• 2010

Intelligent Power Switch (IPS) is a semiconductor device which contains a logic circuit in itself. It has received significant attention as a switching component to substitute the fuse and relay components in common automobile since the internal logic provides the controllability on the loads. However, a control system for the IPS status control and a network system to share the status information of IPS are required to fully exploit the capabilities of IPS. In this paper, we propose a control circuit and algorithm using IPS. Also the communication system between the control systems and IPS components using Control Area network (CAN) are proposed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.768-770
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• 2014

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of multiplication server farms. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.375-378
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• 2013

A reference voltage generator which is insensitive to PVT (process-voltage-temperature) variation necessary for NVM memory IPs such as EEPROM and MTP memories is designed in this paper. The designed BGR (bandgap reference voltage) circuit based on MagnaChip's $0.18{\mu}m$ EEPROM process uses a low-voltage bandgap reference voltage generator of cascode current-mirror type with a wide swing and shows a reference voltage characteristic insensitive to PVT variation. The minimum operating voltage is 1.43V and the VREF sensitivity against VDD variation is 0.064mV/V. Also, the VREF sensitivity against temperature variation is $20.5ppm/^{\circ}C$. The VREF voltage has a mean of 1.181V and its three sigma ($3{\sigma}$) value is 71.7mV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.