• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.73-76
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• 1997

The temperature control system for semiconductor test handler is designed. We controlled the temperature of chamber using 3-wire RTD sensor and MVME EMbedded controller. VxWorks that is a real-time operating system is used and heater is controlled by PWM. Temperature fluctuation of chamber is decreased within 0.3.deg. C, which is about one-half of that of commercial controller.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.77-80
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• 1997

In this paper presented is a temperature controller for a semiconductor test handler. Using ARMAX model and least square method, the chamber model for the design of a controller is identified through experiment. With the identified model an LQG/LTR controller is designed. Experiment with a real test handler demonstrated good performance in that its overshoot is small and response time is fast.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.252-254
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• 1998

본 연구는 반도체 검사 장비를 국산화하는 프로젝트의 일환 중에서 메모리 칩의 무결성을 검사하는데 사용되는 메모리 테스트 장비의 소프트웨어 개발에 중점을 둔 것이다. 기존에 발표된 프로그램은 자체 개발된 것 없이 외국의 프로그램을 들여와 단지 운영만을 하는 수준이었다. 더욱이 프로그램들도 text모드 하에서만 구동되는 프로그램이었다. 하지만, 본 연구에서는 새로운 컴퓨팅 환경에서 운영될 수 있도록 윈도우즈 하에서 GUI(Graphic User Interface)에 기반한 새로운 TDL 컴파일러를 개발하였다. 개발된 프로그램은 Test Data를 기술하는데 더 효과적이었으며 오류를 검사하고 수정하는데도 큰 효과를 가져다 주었다.

• Journal of the Korean Institute of Gas
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• v.28 no.2
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• pp.76-83
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• 2024

In the semiconductor manufacturing process, the Diffusion process generates various reactive by-products. These by-products are deposited inside the pipes of post-processing and exhaust treatment systems, posing a potential risk of substantial dust explosions. In this study, three methods material verification, selection of analysis samples, and risk analysis were employed to address the substances produced during the Diffusion process. Among the materials handled in the Diffusion process, ZrO₂, TEOD, and E-DEOS were identified as raw material capable of generating by-product dust. Test for Minimum Ignition Energy and dust explosion were conducted on the by-products collected from each processing facility. The results indicated that, in the case of MIE, none of the by-products ignited. However, the dust explosion test revealed that ZrO₂ exhibited a maximum pressure of 7.6 bar and K_st value of 73.3 bar·m/s, its explosive hazard. Consequently, to mitigate such risks in semiconductor processes, it is excessive buildup.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Journal of the Korea Society for Simulation
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• v.19 no.1
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• pp.1-11
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• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.321-321
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• 2016

한경오염의 증가에 따라 광촉매 물질을 이용한 환경 정화의 필요성이 대두되고 있다 [1]. 광촉매와 전기화학셀은 빛을 이용하여 다른 에너지를 생산하는 능력을 가지고 있다. 이 전기화학셀의 성능향상을 위해서는 적절한 밴드갭을 이용한 광흡수의 증가, 전자재결합의 감소, 전기화학적 반응 표면의 증가가 필요하다. 산화 아연은 잘 알려진 n형 산화물 반도체로서 좋은 전기적 특성과 광촉매 성능으로 전기화학셀에 적합한 소재이다. 그러나 산화 아연은 액체 전해물질 상에서 안정성이 좋지 못하다 [2]. 이를 해결하기 위해 단층 그래핀 혹은 풀러렌(C60)을 이용하여 산화아연을 코팅하는 방법을 제안하였는데, 풀러렌을 사용 시 단층 그래핀에 비하여 전기화학셀의 전기화학적 반응은 높았으나 안정성은 더 떨어지는 모습을 보였다 [3]. 본 연구에서는 다층 그래핀을 이용하여 전기화학적 반응도 높고 안정성도 높은 산화아연-다층 그래핀 양자점의 합성 및 이를 이용한 전기화학셀 소자의 특성을 연구하였다. X선 회절법, 라만 분광법, 투과 전자 현미경, 광발광 분광기, 시간-분해성 광발광 분광기를 이용하여 산화아연-다층 그래핀 양자점의 특성을 분석하였고, 이를 이용하여 광양극을 제작하여 전기화학적 특성을 관측하였으며 로다민 B 염료를 이용한 분해 테스트를 통하여 광촉매 성능을 확인하였고 사이클 테스트를 통하여 안정성을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1687-1693
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• 2007

Advances in technologies of networking, chip integration, and embedded system have enabled sensor networks applicable to a wide range of areas. Sharing some common characteristics, sensor networks are thus diversified in features depending on their applications. An intelligent and digital home can be one area to establish a particular feature of sensor network. This paper proposes a composite sensor and control network, and discusses its applying to the next generation intelligent and digital home. Development results of the network and a test-bed as a virtual test environment are also presented. The proposed network can not only be efficiently applying to achieve new home intelligences but also provide a sound solution to maintenance and operations of home network or devices.