• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.214-217
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• 2003

상하로 양극 영역이 중첩된 새로운 Si 포토다이오드를 제작하고 이의 전기광학적 특성을 조사하였다. 제작된 소자의 역포화전류와 이상계수는 각각 68pA와 1.8로 나타났으며 -3V 바이어스에서 측정된 접합 커패시턴스는 8.3 pF로 나타났다. 또한 $100mW/cm^2$, AMI 스펙트럼 조건에서 -3V 바이어스 아래 측정된 광전류와 감도특성은 각각 $60\;{\mu}A$와 6 A/W로 나타났다.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.92-92
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• 2000

Ni을 coating 하지 않은 Si 기판에 바이어스를 인가하여 기존의 아이아몬드 결정입자가 아닌 탄소 튜브와 유사한 whisker 형태의 탄소 막을 Hot filament CVD 법으로 증착하였다. 제작된 시료는 SEM, Raman, 그리고 XRD로 형상과 성분, 그리고 결정구조를 분석하여 전계 방출 소자로 이용하기 위한 기본적인 전계방출 특성을 조사하였다. Raman 스펙트럼에 의한 조사 결과 whisker의 구성성분은 비정질 흑연임을 확인하였다. 증착 시 바이어스 전압이 높아짐에 따라 whisker의 형태가 가늘고 길어지는 경향을 보였으며 CH4 농도와 기판 온도가 증가할수록 whisker의 지금이 커지는 현상을 나타내었다. 방출전류밀도는 가늘고 긴 whisker 일수록 증가하는 경향을 나타내었다. 또한 NH3를 첨가한 결과 매우 뾰족한 원뿔의 형태로 증착되었으며 구동전압이 2 V/$\mu$m의 낮은 값을 나타내었다. 따라서 whisker를 전계 방출 소자로 사용할 경우 구성성분이 흑연이며 그 형태가 침상 또는 원뿔이므로 구동전압이 낮아지고 방출 전류가 증가하는 등 향상된 전계 방출 특성을 나타내었다.

• Journal of the Korean Magnetics Society
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• v.15 no.6
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• pp.332-335
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• 2005

Output voltage of the flux-meter has always drift due to the input bias current of non-ideal operational amplifier. In this study we have employed a digital sample and hold amplifier which has no voltage drop to compensate drift of the flux-meter automatically. The drift of the developed flux-meter was smaller than $5{\times}10^{-8}\;Wb/s$ for the integration time constant of $RC=10^{-3}$ s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of Navigation and Port Research
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• v.28 no.3
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• pp.213-219
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• 2004

In this paper, a LNA(Low Noise Amplifier) has been developed, which is operating at L-band i.e., 1452∼1492 MHz for satellite DAB(Digital Audio Brcadcasting) receiver. The LNA is designed to improve input and output reflection coefficient and VSWR(Voltage Standing Wave Ratio) by balanced amplifier. The LNA consists of low noise amplification stage and gain amplification stage, which make a using of GaAs FET ATF-10136 and VNA-25 respectively, and is fabricated by hybrid method. To supply most suitable voltage and current, active bias circuit is designed Active biasing offers the advantage that variations in $V_P$ and $I_{DSS}$ will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets $V_{gs}$ for the desired drain voltage and drain current. The LNA is fabricated on FR-4 substrate with RF circuit and bias circuit, and integrated in aluminum housing. As a reults, the characteristics of the LNA implemented more than 32 dB in gain. 0.2 dB in gain flatness. lower than 0.95 dB in noise figure, 1.28 and 1.43 each input and output VSWR, and -13 dBm in $P_{1dB}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1579-1587
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• 1999

Bias-dependent noise models of $0.2\mu\textrm{m}$ gate length P-HEMT's which are scalable with gate width are proposed. To predict S-parameters of the P-HEMT's the intrinsic parameters except for $\tau$ subtracted the offsets introduced in this paper are normalized to the gate width and then scaled. The small-signal model parameters are expressed as fitting functions of the drain current to $\textrm{I}_{dss}$ ratio and gate width. In addition, to estimate accurately noise parameters the noise temperature $\textrm{T}_{g}$ of the intrinsic resistance, the equivalent noise conductance $\textrm{G}_{ni}$ of the gate current noise source, and the equivalent noise conductance $\textrm{G}_{no}$ of the drain current noise source are adopted as the noise model parameters. The extracted values of $\textrm{T}_{g}$ are nearly independent of drain current and gate width and their average is around the ambient temperature. The extracted values of $\textrm{G}_{ni}$ are small enough to be neglected to the circuit characteristics. From the comparison of the noise model with only $\textrm{G}_{no}$ and that having $\textrm{T}_{g}$, $\textrm{G}_{ni}$ and $\textrm{G}_{no}$ to the measured data it is fund that even the former model is in good agreement with the measured noise parameters. Thus, from a practical point of view the noise model having only the drain current noise source is confirmed as a scalable bias-dependent model.

• Korean Journal of Optics and Photonics
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• v.12 no.3
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• pp.212-218
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• 2001

We experimentally investigated the dependence of extinction ratio and chirp on bias current which was injected into DFB-LD in a directly modulated 2.5 Obitls transmitter. Through the abnormal dispersion transmission, we found that transmission power penalty is minimized at 8-10 dB extinction ratio (bias current at 1.5-1.8 fold above threshold current). Also, we discussed the relation between extinction ratio and self phase modulation (SPM) through the 240 km abnormal dispersion transmission. When SPM takes effect, we obtained the best receiver sensitivity for specific system configuration at 10.4 dB and 8.4 dB extinction ratio, below and above 200km transmission distance, respectively. ively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1121-1133
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• 1998

In this paper, a new method is proposed for a simple andaccurate design of larage-sigal power amplifier using the output current- and volage- waveform analysis. An existing high-efficiency theory, Harmonic Loading, is modified to apply to a real device, and the notion of "actual bias point at large-signal input" is proposed. Based on the proposed theory, 2GHz band poweramplifier is implemented using HEMT device, and the implemented amplifier shows 14dBm output power, 46% drain efficienty, 38% power-added efficiency and 7.8dB gain at 2V bias voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.298-298
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• 2010

최근 태양전지 연구가 활성화 되면서 다양한 종류의 태양전지가 만들어 지고 있다. 이에 따라 태양전지를 정확하게 분석하고 평가하는 방법에 대한 중요성이 커지고 있다. 태양전지의 성능과 품질을 평가하는 방법은 인공태양광조사장치(Solar Simulator)를 사용하여 태양전지의 전류와 전압특성을 측정하는 방법, 양자효율 측정 장치(Quantum Efficiency Measurement System)를 사용하여 태양광의 파장별로 분광반응도를 측정하는 양자효율측정법 등 다양한 방법이 있다. 그 중 양자효율측정법은 태양광의 다양한 파장에 대하여 태양전지가 파장대역마다 어떠한 반응을 하는지 알 수 있고, 그에 따른 태양전지에 사용된 재료의 특성을 알 수 있게 해준다. 일반적으로 양자효율측정은 태양광 아래에서의 상황과 유사한 환경을 만들기 위해 바이어스광을 사용하고, 분광기로 AC광원을 태양전지에 조사하여 측정한다. 바이어스광의 광량 및 AC광원의 주파수에 의해 양자효율 측정결과는 달라질 수 있는데, 이는 태양전지에 사용된 물질에 따라 다른 경향을 보인다. 본 연구에서는 바이어스광과 AC 광원 주파수를 특정한 광주파수대역(100 Hz ~ 1000 Hz)에서 단결정태양전지와 다결정태양전지에 조사하여 측정하였고, 양자효율 대한 영향과 그 결과에 따른 원인을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.