• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.943-950
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• 2005

Recently, many of researches on stream transmission for satisfying each of different real-time transmission condition of the multimedia data that demands various service quality through high-speed networks have been studied actively. In this paper, we design a scheme that discriminately reserves the network resources for the transmission of each multimedia application and propose a bandwidth allocation scheme for improving the utilization ratio of free resources. And we also propose a pipelining scheme for providing flexible real-time transmission. The proposed schemes can be used to support a real-time transmission by applying feedback transmission control method based on receiving buffer for guaranteeing the synchronization conditions requested by the multimedia data. Moreover, we propose a transmission control scheme that can take the amount of network resources down to the minimum amount within the range of permissible error-range under the guarantee with no quality degradation simultaneously when the bottleneck is caused by the network congestion. Finally, we propose a dynamic bandwidth smoothing scheme that can smooth the maximum bandwidth to the demand of each video steam for giving continuous transmission to the delay sensitive video steam between senders and receivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.308-317
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• 2022

Researches are underway to efficiently reduce the size of video data transmitted and stored in the image analysis process using deep learning-based machine vision technology. MPEG (Moving Picture Expert Group) has newly established a standardization project called VCM (Video Coding for Machine) and is conducting research on video encoding for machines rather than video encoding for humans. We are researching a multitask that performs various tasks with one image input. The proposed pipeline does not perform all object detection of each task that should precede object detection, but precedes it only once and uses the result as an input for each task. In this paper, we propose a pipeline for efficient multitasking and perform comparative experiments on compression efficiency, execution time, and result accuracy of the input image to check the efficiency. As a result of the experiment, the capacity of the input image decreased by more than 97.5%, while the accuracy of the result decreased slightly, confirming the possibility of efficient multitasking.

• Journal of Industrial Convergence
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• v.20 no.11
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• pp.19-25
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• 2022

In the development of existing games, it is judged that virtual world production was done by arranging game elements one by one. What is noteworthy here is the question of whether quality virtual worlds were efficiently produced in preparation for investment. In this study, we propose a methodology that can build an efficient virtual world based on the concept of modularization in an unreal engine. First, precedents were analyzed and five reference elements for modularization were extracted. In addition, the concept of an instance production pipeline was proposed by dividing it into four stages, and the minimum-unit instance modules for urban virtual world production were compressed into four. Finally, an urban virtual world constructed based on the minimum unit module and reference elements was implemented and presented. In conclusion, research on the production method centered on this efficiency is thought to be able to focus the time that designers or artists had to spend on production only on ideas and creativity. The limitations of the research are that the basic minimum module is limited to the city, and the derived reference elements and production pipelines have not been verified when implementing them with an unreal engine. Therefore, it is expected that various virtual world creation plans will be derived through more advanced modular research.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.440-448
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• 2011

The needs for the OpenGL-family of the rendering library standards are highly increasing, especially for the graphical human-machine Interface on the various systems including smart phones and personal information devices. Additionally, in the case of safety-critical market for avionics, military, medical and automotive applications, OpenGL SC, the safety critical profile of the OpenGL library plays the major role for the graphical interfaces. In this paper, we represent our OpenGL SC emulation library on the OpenGL 1.x rendering pipeline which is widely available on the existing embedded systems, to provide the features of OpenGL SC standard cost-effectively. Our method can provide the OpenGL SC features at the low development cost on the embedded systems, and its implementation is also one of the fundamental elements for the emulation of embedded systems in the PC environment. Our final result now works on both of Linux-based and VxWORKS systems, showing correct execution results at the reasonable speed.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1450-1457
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• 2011

Currently most of leak detection monitoring systems use digital maps with paying royalties, and this increases the cost of system construction and financial burdens on local self-governing bodies that manage such systems. Moreover, they have inefficiencies in repair and maintenance, functional expansion, and compatibility with other systems. Thus, this study developed a waterworks pipe network monitoring system that pursues low cost and high efficiency using general-purpose maps on the Internet such as google maps. As this system uses highly compatible free maps, it costs less in construction and its hardware requirements are lower than existing systems, and consequently, overall monitoring performance is enhanced and the cost of construction goes down sharply. This study also proposed a method for pipeline DB construction, which can be started together with the construction of the monitoring system, in order to improve the field applicability of the system.

• Journal of Korea Multimedia Society
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• v.16 no.12
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• pp.1427-1438
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• 2013

We have developed a 128-bit stream cipher algorithm composed of the 5-stage pipeline, capable of real-time processing, confidentiality and integrity. The developed stream cipher is a stream cipher algorithm that makes the final 128-bit ciphers through a whitening process after making the ASR 277 bit and SHACAL-2 and applying them to the CFB mode. We have verified the hardware performance of the proposed stream cipher algorithm with Modelsim 6.5d and Quartus II 12.0, and the result shows that the hardware runs at 33.34Mhz(4.27Gbps) at worst case. According to the result, the new cipher algorithm has fully satisfied the speed requirement of wireless Internet and sensor networks, and DRM environment. Therefore, the proposed algorithm with satisfaction of both confidentiality and integrity provides a very useful ideas.