• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.271-272
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• 2014

현재 디지털 시스템 설계가 필요한 모든 유한 상태머신을 설계에는 필수적 밀리 모델이나 무어 모델이 들어간다. 그러나 각각의 기기와 기능에 따라서 밀리 모델과 무어 모델 중 어느 모델이 디지털 논리회로 설계에 효율적인지 판단이 모호한 상황이다. 이를 위해 본 논문에서는 유한 상태머신의 하나인 벤딩머신을 대상으로 밀리 모델과 무어 모델을 사용하여 설계한 후, 설계의 복잡도와 구현 게이트 수를 구하여 각 모델의 효율성에 대해 비교 분석하고자 한다.

• Korean Journal of Logic
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• v.19 no.3
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• pp.341-368
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• 2016

Asserting a sentence of the form "p but I do not believe that p" sounds inappropriate, and even absurd or contradictory. The problem that Moore's paradox raises is to explain why asserting such a sentence is absurd despite the fact that there is apparently no logical contradiction in it. Many of the influential accounts of Moore's paradox try to locate its source in the nature of belief or in the nature of assertion. In this paper, I argue that these accounts are not satisfactory, and develop and defend a novel account. According to this account, the source of Moore's paradox should be located in self-reference. Self-reference is constituted by a certain disposition to form second-order beliefs. A subject who is ready to assert "p but I do not believe p" fails to conform to the disposition that is constitutive of self-reference, while at the same time referring to the relevant individual with "I."

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• 발명특허
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• v.5 no.12 s.58
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• pp.45-45
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• 1980

• 정보화사회
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• s.2
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• pp.47-48
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• 1988

• Korean Journal of Logic
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• v.17 no.2
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• pp.287-322
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• 2014

We put forward a scheme of the theory of analysis, and G. E. Moore's theory of analysis is reconstructed. As C. H. Langford pointed out, Moore's theory commits to the paradox of analysis which says that if a analysis is correct then it is not informative, and if it is informative it is not correct. For, according to his theory, analysing statement is necessarily true identity statement and have some information. Moorean responses which is given by Max Black, Raymond Bradley and Norman Swartz, and Wilfrid Sellars rely on the distinction between the information about concepts and linguistic entity. These approaches are deficient in dealing properly with the difference in concepts as analysandum and analysans. Also, non-Moorean resolutions asserted by Myers, King, Black, and Earl are examined.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.254-263
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• 1995

In this paper we discuss Moore and Mealy-model Time-stationary control schemes of pipelined data paths of Application Specific, Integrated Circuits (ASICs). We developed a method to synthesize both a Moore and a Mealy-style Finite State Machine(FSM) controller specifications given a pipelined data path with conditional branches. The control synthesis task consists of the generation of control specification and the FSM synthesis. The control specification procedure generates a FSM specification in the form of a state table. The different partitioning schemes are applied to each FSM controller so as to minimize the total area. Experimental results show the characteristics of the two different control styles and the effects of these two models on cost and performance.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.37-52
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• 2013

무어의 법칙에 따르면, 반도체의 집적도 2년마다 2배씩 증가한다고 한다. 무어의 법칙은 지금까지는 집적회로 기술의 발전을 잘 예측했다. 하지만 트랜지스터의 사이즈를 줄일수록 누수전류와 회로의 저항을 조절하기 어렵기 때문에 트랜지스터의 소형화에는 한계가 있다. 우리는 곧 무어의 법칙의 한계를 맞이할 것이다. 그래서 트랜지스터를 더욱 소형화시키기 위해서는 bottom-up analysis가 필요한 시점이다. Top-down analysis가 초기의 커다란 트랜지스터에서 점점 소형화를 시켜 작은 트랜지스터를 만든다는 개념인 반면, Bottom-up analysis는 처음부터 작은 분자를 조작하여 트랜지스터와 같은 성질을 띄도록 만드는 개념이다. 분자가 기억소자로서 이용되려면 저항이 다른 2가지 안정한 상태가 필요하다. 이번 연구에서 나는 기억소자를 디자인 하기 위하여 high spin state와 low spin state 두 가지 안정한 상태를 가지는 spin crossover complex를 이용하기로 했다. 이전의 연구에서 spin crossover 는 전기장을 이용해서도 유도될 수 있다고 확신하였고, 이를 이용해서 기억소자를 디자인하기로 하였다. 이번 연구를 위해서 symmetry를 가지는 octahedral spin crossover complex를 디자인하였고 이를 '기억 분자'라고 명명했다. 그리고 이 분자의 high spin state와 low spin state가 전기장을 이용하여 서로 바뀔 수 있는지 가능성을 DFT with B3LYP functional을 이용해서 비교했다. 그 결과로 전기장을 이용하여 기억분자의 spin crossover을 일으킬 수는 있지만 abnormally strong electric field를 써야 한다는 사실을 알아냈다. 이번 연구를 토대로 추후의 연구를 위해, 기억소자가 되기 위하여 분자가 어떤 특징을 만족시켜야 하는지를 분석했다.

• The Inventors News
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• no.31
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• pp.7-7
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• 2005

우에조 히로지의 `종이 꼬리표` - 찰스 스틸웰의 `종이 쇼핑백` - 휴그 무어의 `종이컵` - 등받이 및 붙박이식 접이 기능을 가진 소파