• 대한기계학회논문집B
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• 제27권7호
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• pp.829-836
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• 2003

Understanding of heat generation in semiconductor devices is important in the thermal management of integrated circuits and in the analysis of the device physics. Scanning thermal microscope was used to measure the temperature and the electric potential distribution on the cross-section of an operating metal-oxide-semiconductor field-effect transistor (MOSFET). The temperature distributions were measured both in DC and AC modes in order to take account of the leakage current. The measurement results showed that as the drain bias was increased the hot spot moved to the drain. The density of the iso-potential lines near the drain increased with the increase in the drain bias.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.26-32
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• 1998

We have studied how the characteristics degradation between effective mobility and field effect mobility of gate channel in p-MOSFET's affects the gate channel length being follow by increased stress time and increased drain-source voltage stress. The experimental results between effective and field-effect mobility were analyzed that the measurement data are identical at the point of minimum slope in threshold voltage, the other part is different, that is, the effective mobility it the faster than the field-effect mobility. Also, It was found that the effective and field-effect mobility. Also, It was found that the effective and field-effect mobility of p-MOSFET's with short channel are increased by decreased channel length, increased stress time and increased drain-source voltage stress.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권5호
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• pp.270-277
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• 2000

A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

• 대한기계학회논문집B
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• 제30권1호
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• pp.41-47
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• 2006

High resolution dopant profiling in semiconductor devices has been an intense research topic because of its practical importance in semiconductor industry. Although several techniques have already been developed. it still requires very expensive tools to achieve nanometer scale resolution. In this study we demonstrated a novel dopant profiling technique with nanometer resolution using very simple setup. The newly developed technique measures the thermoelectric voltage generated in the contact point of the SPM probe tip and MOSFET surface instead of electrical signals widely adopted in previous techniques like Scanning Capacitance Microscopy. The spatial resolution of our measurement technique is limited by the size of contact size between SPM probe tip and MOSFET surface and is estimated to be about 10 nm in this experiment.

• 한국정보통신학회논문지
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• 제16권1호
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• pp.127-132
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• 2012

본 논문에서는, 초고집적 MOSFET를 위한 향상된 얕은 트랜치 접합 격리에서 높은 임계전압을 위한 활성영역 부분의 제안된 구조의 가장자리 효과를 시뮬레이션 하였다. 얕은 접합 격리는 트랜지스터와 트랜지스터 사이에서 전기적 격리를 하기 때문에 쌍보형-모스 기술에서 중요한 공정 요소이다. 시뮬레이션 결과, 얕은 트랜치 접합 격리 구조가 수동적인 전기적 기능 일지라도, 소자의 크기가 감소됨에 따라서, 초대규모 집적회로 공정의 응용에서 제안된 얕은 트랜치 격리 구조에서 전기적 특성의 영향은 전위차, 전계와 포화 임계 전압에서 높게 나타났다.