• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.7
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• pp.829-836
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• 2003

Understanding of heat generation in semiconductor devices is important in the thermal management of integrated circuits and in the analysis of the device physics. Scanning thermal microscope was used to measure the temperature and the electric potential distribution on the cross-section of an operating metal-oxide-semiconductor field-effect transistor (MOSFET). The temperature distributions were measured both in DC and AC modes in order to take account of the leakage current. The measurement results showed that as the drain bias was increased the hot spot moved to the drain. The density of the iso-potential lines near the drain increased with the increase in the drain bias.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.26-32
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• 1998

We have studied how the characteristics degradation between effective mobility and field effect mobility of gate channel in p-MOSFET's affects the gate channel length being follow by increased stress time and increased drain-source voltage stress. The experimental results between effective and field-effect mobility were analyzed that the measurement data are identical at the point of minimum slope in threshold voltage, the other part is different, that is, the effective mobility it the faster than the field-effect mobility. Also, It was found that the effective and field-effect mobility. Also, It was found that the effective and field-effect mobility of p-MOSFET's with short channel are increased by decreased channel length, increased stress time and increased drain-source voltage stress.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.270-277
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• 2000

A new Lateral Trench-MOS Bipolar-Mode Field-Effect Transistor(LTMBMFET) is proposed and verified by MEDICI simulation. By using a trench MOS structure, the proposed device can enhance the current gain without sacrificing other device characteristics such as the breakdown voltage. The channel region of the proposed device is formed between the trench MOS structure. So the effect of the substrate voltage is negligible when compared with the conventional device which has a channel region between the gate junction and the buried oxide layer.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.1 s.244
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• pp.41-47
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• 2006

High resolution dopant profiling in semiconductor devices has been an intense research topic because of its practical importance in semiconductor industry. Although several techniques have already been developed. it still requires very expensive tools to achieve nanometer scale resolution. In this study we demonstrated a novel dopant profiling technique with nanometer resolution using very simple setup. The newly developed technique measures the thermoelectric voltage generated in the contact point of the SPM probe tip and MOSFET surface instead of electrical signals widely adopted in previous techniques like Scanning Capacitance Microscopy. The spatial resolution of our measurement technique is limited by the size of contact size between SPM probe tip and MOSFET surface and is estimated to be about 10 nm in this experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.