• Title/Summary/Keyword: 모바일 캐시 메모리

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A Cache-based Reconfigurable Accelerator in Die-stacked DRAM (3차원 구조 DRAM의 캐시 기반 재구성형 가속기)

  • Kim, Yongjoo
    • KIPS Transactions on Computer and Communication Systems
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    • v.4 no.2
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    • pp.41-46
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    • 2015
  • The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

The Analysis and Design of Thread Model for Java Virtual Machine (자바가상머신 쓰레드 모델 분석 및 설계)

  • 유용선;박윤미;류현수;이철훈
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10a
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    • pp.625-627
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    • 2004
  • 최근 들어 인터넷의 발달과 더불어 PDA, 핸드폰과 같은 모바일 디바이스와 다양한 정보가전용 기기들에 네트워크 기반의 자바기술이 적용되고 있으며, 이러한 자바 기술을 사용함으로써 플랫폼 독립성 이식성, 보안성, 이동성 둥의 장점을 얻을 수 있다. 그러나, 자바로 작성된 응용프로그램은 C, C++로 작성된 응용프로그램 보다 수행속도가 느리다는 단점이 있다. 이러한 문제점을 해결하기 위해서는 자바가상머신의 성능향상이 필수적이다. 지금까지 메모리 관리를 위한 가비지 컬렉션, 소프트웨어나 하드웨어를 이용한 바이트 코드 변환, 인라인캐시(inline-cache)를 사용한 접근 속도 향상 등 많은 부분에서 활발한 연구가 진행되고 있다. 본 논문에서는 모바일 플랫폼에서 동작하는 KVM(kilo-virtual machine)의 성능향상을 위한 쓰레드 구조를 분석하고 설계한다.

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Multi-layer Caching Scheme Considering Sub-graph Usage Patterns (서브 그래프의 사용 패턴을 고려한 다중 계층 캐싱 기법)

  • Yoo, Seunghun;Jeong, Jaeyun;Choi, Dojin;Park, Jaeyeol;Lim, Jongtae;Bok, Kyoungsoo;Yoo, Jaesoo
    • The Journal of the Korea Contents Association
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    • v.18 no.3
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    • pp.70-80
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    • 2018
  • Due to the recent development of social media and mobile devices, graph data have been using in various fields. In addition, caching techniques for reducing I/O costs in the process of large capacity graph data have been studied. In this paper, we propose a multi-layer caching scheme considering the connectivity of the graph, which is the characteristics of the graph topology, and the history of the past subgraph usage. The proposed scheme divides a cache into Used Data Cache and Prefetched Cache. The Used Data Cache maintains data by weights according to the frequently used sub-graph patterns. The Prefetched Cache maintains the neighbor data of the recently used data that are not used. In order to extract the graph patterns, their past history information is used. Since the frequently used sub-graphs have high probabilities to be reused, they are cached. It uses a strategy to replace new data with less likely data to be used if the memory is full. Through the performance evaluation, we prove that the proposed caching scheme is superior to the existing cache management scheme.

Separate Factor Caching Scheme for Mobile Web Service (모바일 웹 서비스를 위한 요소분할 캐싱 기법)

  • Sim, Kun-Jung;Kang, Eui-Sun;Kim, Jong-Keun;Ko, Hee-Ae;Lim, Young-Hwan
    • The KIPS Transactions:PartD
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    • v.14D no.4 s.114
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    • pp.447-458
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    • 2007
  • The objective of this study is to provide faster mobile web service by improving performance of Contents Cache used for mobile web service in the existing Mobile Gate System. It was found that two elements existed in Mark-Up page transcoded by Contents Generator. One of the elements was dependent only on the requested DIDL page and Mark-Up type. The other was dependent on each of the requested DIDL page, Mark-Up type, size of mobile display 모바일 장치 to request service, type of images available and color depth count of the images available. The conventional Contents Cache saved the entire Mark-Up page to hold both of the two elements. This caused the problem where storage space was not effectively used because reusable elements were repetitively saved in cache memory domain due to change in one of the elements even though all the other elements were the same. As a result, a larger number of transcoded Mark-Up pages could not be saved in the same cache memory size. Therefore, in this study, Mark-Up pages transcoded by Contents Generator were divided into two elements and were separately saved. Also, in order to respond to the demand for replacing data in cache with new data, this study applied two algorithms of LFU and LRU. This study proposed the method to implement cache performance of faster speed by enabling to save more number of the transcoded Mark-Up pages in the same cache storage space.

Web-Based Distributed Visualization System for Large Scale Geographic Data (대용량 지형 데이터를 위한 웹 기반 분산 가시화 시스템)

  • Hwang, Gyu-Hyun;Yun, Seong-Min;Park, Sang-Hun
    • Journal of Korea Multimedia Society
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    • v.14 no.6
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    • pp.835-848
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    • 2011
  • In this paper, we propose a client server based distributed/parallel system to effectively visualize huge geographic data. The system consists of a web-based client GUI program and a distributed/parallel server program which runs on multiple PC clusters. To make the client program run on mobile devices as well as PCs, the graphical user interface has been designed by using JOGL, the java-based OpenGL graphics library, and sending the information about current available memory space and maximum display resolution the server can minimize the amount of tasks. PC clusters used to play the role of the server access requested geographic data from distributed disks, and properly re-sample them, then send the results back to the client. To minimize the latency happened in repeatedly access the distributed stored geography data, cache data structures have been maintained in both every nodes of the server and the client.

Analyses of the Effect of System Environment on Filebench Benchmark (시스템 환경이 Filebench 벤치마크에 미치는 영향 분석)

  • Song, Yongju;Kim, Junghoon;Kang, Dong Hyun;Lee, Minho;Eom, Young Ik
    • Journal of KIISE
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    • v.43 no.4
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    • pp.411-418
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    • 2016
  • In recent times, NAND flash memory has become widely used as secondary storage for computing devices. Accordingly, to take advantage of NAND flash memory, new file systems have been actively studied and proposed. The performance of these file systems is generally measured with benchmark tools. However, since benchmark tools are executed by software simulation methods, many researchers get non-uniform benchmark results depending on the system environments. In this paper, we use Filebench, one of the most popular and representative benchmark tools, to analyze benchmark results and study the reasons why the benchmark result variations occur. Our experimental results show the differences in benchmark results depending on the system environments. In addition, this study substantiates the fact that system performance is affected mainly by background I/O requests and fsync operations.

Efficient DRAM Buffer Access Scheduling Techniques for SSD Storage System (SSD 스토리지 시스템을 위한 효율적인 DRAM 버퍼 액세스 스케줄링 기법)

  • Park, Jun-Su;Hwang, Yong-Joong;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.48-56
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    • 2011
  • Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.